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参数资料
| 型号： | ESD7008MUTAG |
| 厂商： | ON Semiconductor |
| 文件页数： | 3/10页 |
| 文件大小： | 0K |
| 描述： | IC DIODE LOW CAP ESD 18UDFN |
| 标准包装： | 3,000 |
| 电压 - 反向隔离（标准值）： | 5V |
| 电压 - 击穿： | 5.5V |
| 电极标记： | 8 通道阵列 - 双向 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 18-UFDFN 裸露焊盘 |
| 供应商设备封装： | 18-UDFN（5.5x1.5） |
| 包装： | 带卷 (TR) |
ESD7008
ELECTRICAL CHARACTERISTICS (T A = 25 ° C unless otherwise specified)
Parameter
Reverse Working Voltage
Breakdown Voltage
Symbol
V RWM
V BR
Conditions
I/O Pin to GND (Note 1)
I T = 1 mA, I/O Pin to GND
Min
5.5
Typ
6.7
Max
5.0
Unit
V
V
Reverse Leakage Current
Clamping Voltage (Note 1)
Clamping Voltage (Note 2)
Clamping Voltage
TLP (Note 3)
See Figures 8 through 11
I R
V C
V C
V C
V RWM = 5 V, I/O Pin to GND
I PP = 1 A, I/O Pin to GND (8 x 20 m s pulse)
IEC61000 ? 4 ? 2, ± 8 kV Contact
I PP = ± 8 A
I PP = ± 16 A
See Figures 3 and 4
13.2
18.2
1.0
10
m A
V
V
Junction Capacitance
Junction Capacitance
Difference
C J
D C J
V R = 0 V, f = 1 MHz between I/O Pins and GND
V R = 0 V, f = 1 MHz between I/O Pins and GND
0.12
0.02
0.15
pF
pF
1. Surge current waveform per Figure 7.
2. For test procedure see Figures 5 and 6 and application note AND8307/D.
3. ANSI/ESD STM5.5.1 ? Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z 0 = 50 W , t p = 100 ns, t r = 4 ns, averaging window; t 1 = 30 ns to t 2 = 60 ns.
90
80
70
60
50
40
30
20
10
0
0
? 10
? 20
? 30
? 40
? 10
? 20
0
20
40
60 80
100
120
140
? 50
? 20
0
20
40
60 80
100
120
140
TIME (ns)
Figure 3. IEC61000 ? 4 ? 2 +8 KV Contact
Clamping Voltage
http://onsemi.com
3
TIME (ns)
Figure 4. IEC61000 ? 4 ? 2 ? 8 KV Contact
Clamping Voltage
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