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| 型号： | EVAL-AD5162SDZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 14/20页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD5162 |
| 标准包装： | 1 |
| 主要目的： | 数字电位器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD5162 |
| 主要属性： | 2 通道，256 位置 |
| 次要属性： | SPI 接口 |
| 已供物品： | 板，CD |
AD5162
Rev. C | Page 3 of 20
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS: 2.5 k VERSION
VDD = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; 40°C < TA < +125°C; unless otherwise noted.
Table 1.
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity2
R-DNL
R
WB, VA = no connect
2
±0.1
+2
LSB
Resistor Integral Nonlinearity2
R-INL
R
WB, VA = no connect
14
±2
+14
LSB
Nominal Resistor Tolerance3
R
AB
T
A = 25°C
20
+55
%
Resistance Temperature Coefficient
(R
AB/RAB )/T
V
AB = VDD, wiper = no connect
35
ppm/°C
Wiper Resistance
R
WB
Code = 0x00, V
DD = 5 V
160
200
DC CHARACTERISTICS—POTENTIOMETER
DIVIDER MODE4
Differential Nonlinearity5
DNL
1.5
±0.1
+1.5
LSB
Integral Nonlinearity5
INL
2
±0.6
+2
LSB
Voltage Divider Temperature
Coefficient
(V
W/VW)/T
Code = 0x80
15
ppm/°C
Full-Scale Error
V
WFSE
Code = 0xFF
14
5.5
0
LSB
Zero-Scale Error
V
WZSE
Code = 0x00
0
4.5
12
LSB
RESISTOR TERMINALS
Voltage Range6
V
A, VB, VW
GND
V
DD
V
Capacitance A, B7
C
A, CB
f = 1 MHz, measured to GND,
code = 0x80
45
pF
Capacitance W7
C
W
f = 1 MHz, measured to GND,
code = 0x80
60
pF
Common-Mode Leakage
I
CM
V
A = VB = VDD/2
1
nA
DIGITAL INPUTS AND OUTPUTS
Input Logic High
V
IH
V
DD = 5 V
2.4
V
Input Logic Low
V
IL
V
DD = 5 V
0.8
V
Input Logic High
V
IH
V
DD = 3 V
2.1
V
Input Logic Low
V
IL
V
DD = 3 V
0.6
V
Input Current
I
IL
V
IN = 0 V or 5 V
±1
A
Input Capacitance7
C
IL
5
pF
POWER SUPPLIES
Power Supply Range
V
DD RANGE
2.7
5.5
V
Supply Current
I
DD
V
IH = 5 V or VIL = 0 V
3.5
6
A
Power Dissipation8
P
DISS
V
IH = 5 V or VIL = 0 V, VDD = 5 V
30
W
Power Supply Sensitivity
PSS
V
DD = 5 V ± 10%, code = midscale
±0.02
±0.08
%/%
DYNAMIC CHARACTERISTICS9
Bandwidth, 3 dB
BW
Code = 0x80
4.8
MHz
Total Harmonic Distortion
THD
W
V
A = 1 V rms, VB = 0 V, f = 1 kHz
0.1
%
V
W Settling Time
t
S
V
A = 5 V, VB = 0 V, ±1 LSB error band
1
s
Resistor Noise Voltage Density
e
N_WB
R
WB = 1.25 k, RS = 0
3.2
nV/√Hz
1 Typical specifications represent average readings at 25°C and V
DD = 5 V.
2 Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from the ideal between successive tap positions. Parts are guaranteed monotonic.
3 V
A = VDD, VB = 0 V, wiper (VW) = no connect.
4 Specifications apply to all VRs.
5 INL and DNL are measured at V
W with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
6 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
7 Guaranteed by design, but not subject to production test.
8 P
DISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
9 All dynamic characteristics use V
DD = 5 V.
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