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参数资料
| 型号： | EVAL-AD5535EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 4/16页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD5535 |
| 产品培训模块： | DAC Architectures |
| 标准包装： | 1 |
| DAC 的数量： | 32 |
| 位数： | 14 |
| 采样率（每秒）： | 1.2M |
| 数据接口： | 串行 |
| 设置时间： | 65µs |
| DAC 型： | 电压 |
| 工作温度： | -40°C ~ 85°C |
| 已供物品： | 板，CD |
| 已用 IC / 零件： | AD5535 |
| 相关产品： | AD5535ABCZ-ND - IC DAC 14BIT 32CHAN 124CSPBGA |
AD5535
Rev. A | Page 12 of 16
FUNCTIONAL DESCRIPTION
A4 to A0 Bits
The AD5535 consists of a 32 channel, 14-bit DAC with 200 V
high voltage amplifiers in a single 15 mm × 15 mm CSP_BGA
package. The output voltage range is programmable via the
REF_IN pin. The output range is 0 V to 50 V when REF_IN =
1 V, and 0 V to 200 V when REF_IN = 4 V. Communication
to the device is through a serial interface operating at clock
rates of up to 30 MHz, which is compatible with DSP and
microcontroller interface standards. A 5-bit address and a
14-bit data-word are loaded into the AD5535 input register
via the serial interface. The channel address is decoded, and
the data-word is converted into an analog output voltage for
this channel.
These bits can address any one of the 32 channels. A4 is the
MSB of the address; A0 is the LSB.
DB13 to DB0 Bits
These bits are used to write a 14-bit word into the addressed
DAC register.
Figure 2 is the timing diagram for a serial write to the AD5535.
The serial interface works with both a continuous and a discon-
tinuous serial clock. The first falling edge of SYNC resets the
serial clock counter to ensure that the correct number of bits are
shifted into the serial shift register. Any further edges on SYNC
are ignored until the correct number of bits are shifted in. Once
19 bits have been shifted in, the SCLK is ignored. For another
serial transfer to take place, the counter must be reset by the
falling edge of
At power-on, all the DAC registers are loaded with 0s.
DAC SECTION
The architecture of each DAC channel consists of a resistor
string DAC, followed by an output buffer amplifier operating
with a nominal gain of 50. The voltage at the REF_IN pin
provides the reference voltage for the corresponding DAC. The
input coding to the DAC is straight binary, and the ideal DAC
output voltage is given by
SYNC. The user must allow 200 ns (minimum)
between successive writes.
A4
A3
A2
A1
A0
DB13–DB0
MSB
LSB
05068-010
Figure 16. Serial Data Format
14
_
2
50
D
V
IN
REF
OUT
×
=
MICROPROCESSOR INTERFACING
AD5535-to-ADSP-21xx Interface
where D is the decimal equivalent (0 to 16,383) of the binary
code, which is loaded to the DAC register.
The ADSP-21xx family of DSPs is easily interfaced to the
AD5535 without the need for extra logic. A data transfer is
initiated by writing a word to the TX register after SPORT is
enabled. In a write sequence, data is clocked out upon each
rising edge of the DSP’s serial clock and clocked into the
AD5535 upon the falling edge of its SCLK. The easiest way to
provide the 19-bit data-word required by the AD5535 is to
transmit two 10-bit data-words from the ADSP-21xx. Ensure
that the data is positioned correctly in the TX register so that
the first 19 bits transmitted contain valid data.
The output buffer amplifier is specified to drive a load of 1 MΩ
and 200 pF. The linear output voltage range for the output
amplifier is from 7 V to VPP 10 V. The amplifier output band-
width is typically 5 kHz, and is capable of sourcing 700 μA and
sinking 2.8 mA. Settling time for a to full-scale step change
is typically 30 μs with no load and 65 μs with a 200 pF load.
RESET FUNCTION
The reset function on the AD5535 can be used to reset all nodes
on the device to their power-on reset condition. All the DACs
are loaded with 0s, and all registers are cleared. The reset
function is implemented by taking the
Set up the SPORT control register as shown in
Table 6.
Name
Value
Description
RESET pin low.
TFSW
1
Alternate framing
SERIAL INTERFACE
The serial interface is controlled by three pins:
SYNC is the frame synchronization pin for the serial interface.
SCLK is the serial clock input. This pin operates at clock
speeds of up to 30 MHz.
D
IN
is the serial data input. Data must be valid upon the
falling edge of SCLK.
To update a single DAC channel, a 19-bit data-word is written
to the AD5535 input register.
INVTFS
1
Active low frame signal
DTYPE
00
Right justify data
ISCLK
1
Internal serial clock
TFSR
1
Frame every word
ITFS
1
Internal framing signal
SLEN
1001
10-bit data-word
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