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参数资料
| 型号： | EVAL-AD7264EDZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 8/29页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD7264 |
| 标准包装： | 1 |
| ADC 的数量： | 1 |
| 位数： | 14 |
| 采样率（每秒）： | 1M |
| 数据接口： | 串行 |
| 输入范围： | 5 Vpp |
| 在以下条件下的电源（标准）： | 120mW @ 1MSPS |
| 工作温度： | -40°C ~ 105°C |
| 已用 IC / 零件： | AD7264 |
| 已供物品： | 板 |
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Data Sheet
AD7264
Rev. B | Page 15 of 28
THEORY OF OPERATION
CIRCUIT INFORMATION
The AD7264 is a fast, dual, simultaneous sampling, differential,
14-bit, serial ADCs. The AD7264 contains two on-chip diffe-
rential programmable gain amplifiers, two track-and-hold
amplifiers, and two successive approximation analog-to-digital
converters with a serial interface with two separate data output
pins. The AD7264 also includes four on-chip comparators. The
part is housed in a 48-lead LFCSP or 48-lead LQFP package,
offering the user considerable space-saving advantages over
alternative solutions. The AD7264 requires a low voltage 5 V ±
5% AVCC to power the ADC core and supply the digital power, a
2.7 V to 5.25 V CA_CBVCC, CC_CDVCC supply for the comparators,
and a 2.7 V to 5.25 V VDRIVE supply for interface power.
The on-board PGA allows the user to select from 14 program-
mable gain stages: ×1, ×2, ×3, ×4, ×6, ×8, ×12, ×16, ×24, ×32,
×48, ×64, ×96, and ×128. The PGA accepts fully differential
analog signals. The gain can be selected either by setting the
logic state of the G0 to G3 pins or by programming the control
register.
The serial clock input accesses data from the part while also
providing the clock source for each successive approximation
ADC. The AD7264 has an on-chip 2.5 V reference that can be
disabled when an external reference is preferred. If the internal
reference is used elsewhere in a system, the output from VREFA
and VREFB must first be buffered. If the internal reference is the
preferred option, the user must tie the REFSEL pin to a logic
high voltage. Alternatively, if REFSEL is tied to GND, an
external reference can be supplied to both ADCs through the
The AD7264 also features a range of power-down options to
allow the user great flexibility with the independent circuit
components while allowing for power savings between conver-
sions. The power-down feature is implemented via the control
register or the PD0 to PD2 pins, as described in the Control
Register section.
COMPARATORS
The AD7264 has four on-chip comparators. Comparator A and
Comparator B have ultralow power consumption, with static
power consumption typically less than 10 μW with a 3.3 V
supply. Comparator C and Comparator D feature very fast
propagation delays of 130 ns for a 200 mV differential overdrive.
These comparators have push-pull output stages that operate
from the VDRIVEsupply. This feature allows operation with a
minimum amount of power consumption.
Each pair of comparators operates from its own independent
supply, CA_CBVCC or CC_CDVCC. The comparators are specified
for supply voltages from 2.7 V to 5.25 V. If desired, CA_CBVCC
and CC_CDVCC can be tied to the AVCC supply. The four compa-
rators on the AD7264 are functional with CA_CBVCC, CC_CDVCC
greater than or equal to 1.8 V. However, no specifications are
guaranteed for comparator supplies less than 2.7 V. The wide
range of supply voltages ensures that the comparators can be
used in a variety of battery backup modes.
The four on-chip comparators on the AD7264 are ideally suited
for monitoring signals from pole sensors in motor control
systems. The comparators can be used to monitor signals from
Hall effect sensors or the inner tracks from an optical encoder.
One of the comparators can be used to count the index marker
or z marker, which is used on startup to place the motor in a
known position.
OPERATION
The AD7264 has two successive approximation ADCs, each
based around two capacitive DACs and two programmable gain
amplifiers.
The ADC itself comprises control logic, a SAR, and two capacitive
DACs. The control logic and the charge redistribution DACs are
used to add and subtract fixed amounts of charge from the sam-
pling capacitor amplifiers to bring the comparator back into a
balanced condition. When the comparator is rebalanced, the
conversion is complete. The control logic generates the ADC
output code.
Each ADC is preceded by its own programmable gain stage. The
PGA features high analog input impedance, true differential
analog inputs that allow the output from any source or sensor to
be connected directly to the PGA inputs without any requirement
for additional external buffering. The variable gain settings ensure
that the device can be used for amplifying signals from a variety
of sources. The AD7264 offers the flexibility to choose the most
appropriate gain setting to utilize the wide dynamic range of
the device.
ANALOG INPUTS
Each ADC in the AD7264 has two high impedance differential
analog inputs. Figure 24 shows the equivalent circuit of the
analog input structure of the AD7264. It consists of a fully
differential input amplifier that buffers the analog input signal
and provides the gain selected by using the gain pins.
The two diodes provide ESD protection. Care must be taken to
ensure that the analog input signals never exceed the supply rails by
more than 300 mV. This causes these diodes to become forward-
biased and to start conducting current into the substrate. These
diodes can conduct up to 10 mA without causing irreversible
damage to the part. The C1 capacitors in Figure 24 are typically
5 pF and can primarily be attributed to pin capacitance.
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