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参数资料
| 型号： | EVAL-AD7608EDZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 18/32页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD7608 |
| 标准包装： | 1 |
| ADC 的数量： | 8 |
| 位数： | 18 |
| 采样率（每秒）： | 200k |
| 数据接口： | DSP，MICROWIRE?，并联，QSPI?，串行，SPI? |
| 输入范围： | ±10 V |
| 在以下条件下的电源（标准）： | 100mW @ 200kSPS |
| 工作温度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7608 |
| 已供物品： | 板 |
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Data Sheet
AD7608
Rev. A | Page 25 of 32
SERIAL INTERFACE (PAR/SER SEL = 1)
To read data back from the AD7608 over the serial interface,
the
AA
PAREE
AA
/SER SEL pin should be tied high. The
AA
CSEE
AA
and SCLK
signals are used to transfer data from the AD7608. The AD7608
has two serial data output pins, DOUTA, and DOUTB. Data can be
read back from the AD7608 using one or both of these DOUT
lines. For the AD7608, conversion results from Channel V1 to
Channel V4 first appear on DOUTA while conversion results from
Channel V5 to Channel V8 first appear on DOUTB.
The
AA
CSEE
AA
falling edge takes the data output lines (DOUTA
and DOUTB) out of three-state and clocks out the MSB of
the conversion result. The rising edge of SCLK clocks all
subsequent data bits onto the serial data outputs, DOUTA
and DOUTB. The
AA
CSEE
AA
input can be held low for the entire
serial read, or it can be pulsed to frame each channel read
of 18 SCLK cycles.
Figure 43 shows a read of eight simultaneous conversion results
using two DOUT lines on the AD7608. In this case, a 72 SCLK
transfer is used to access data from the AD7608 and
EE
AA
is held
low to frame the entire 72 SCLK cycles. Data can also be clocked
out using just one DOUT line, in which case DOUTA is recommended
to access all conversion data as the channel data is output in
ascending order. For the AD7608 to access all eight conversion
results on one DOUT line, a total of 144 SCLK cycles are required.
These 144 SCLK cycles can be framed by one
AA
CSEE
AA
signal or each
group of 18 SCLK cycles can be individually framed by the
AA
CSEE
AA
signal. The disadvantage of using just one DOUT line is that the
throughput rate is reduced if reading after conversion. The
unused DOUT line should be left unconnected in serial mode.
For the AD7608, if DOUTB is used as a single DOUT line, the
channel results will output in the following order: V5, V6, V7,
V8, V1, V2, V3, V4; however, the FRSTDATA indicator returns
low once V5 is read on DOUTB.
CS
Figure 6 shows the timing diagram for reading one channel of
data, framed by the
EE
AA
signal, from the AD7608 in serial mode.
The SCLK input signal provides the clock source for the serial
read operation.
AA
CSEE
AA
goes low to access the data from the AD7608.
The falling edge of
AA
CSEE
AA
takes the bus out of three-state and
clocks out the MSB of the 18-bit conversion result. This MSB
is valid on the first falling edge of the SCLK after the
AA
CSEE
AA
falling
edge. The subsequent 17 data bits are clocked out of the AD7608
on the SCLK rising edge. Data is valid on the SCLK falling edge.
Eighteen clock cycles must be provided to the AD7608 to access
each conversion result.
CS
The FRSTDATA output signal indicates when the first channel,
V1, is being read back. When the
AA
CSEE
AA
input is high, the FRSTDATA
output pin is in three-state. In serial mode, the falling edge of
AA
CSEE
AA
takes FRSTDATA out of three-state and sets the FRSTDATA
pin high indicating that the result from V1 is available on the
DOUTA output data line. The FRSTDATA output returns to a
logic low following the 18th SCLK falling edge. If all channels
are read on DOUTB, the FRSTDATA output does not go high
when V1 is output on the serial data output pin. It only goes
high when V1 is available on DOUTA (and this is when V5 is
available on DOUTB).
READING DURING CONVERSION
Data can be read from the AD7608 while BUSY is high and
conversions are in progress. This has little effect on the
performance of the converter and allows a faster throughput
rate to be achieved. A parallel or serial read may be performed
during conversions and when oversampling may or may not
be in use. Figure 3 shows the timing diagram for reading while
BUSY is high in parallel or serial mode. Reading during conver-
sions allows the full throughput rate to be achieved when using
the serial interface with a VDRIVE of 3.3 V to 5.25 V.
Data can be read from the AD7608 at any time other than on
the falling edge of BUSY because this is when the output data
registers get updated with the new conversion data. Time t6, as
outlined in Table 3, should be observed in this condition.
V1
V4
V2
V3
V5
V8
V6
V7
SCLK
DOUTA
DOUTB
CS
72
08938-
041
Figure 43. AD7608 Serial Interface with two DOUT Lines
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