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| 型号： | EVAL-AD7610EDZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 17/32页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD7610 |
| 标准包装： | 1 |
| 系列： | * |
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AD7610
Data Sheet
Rev. A | Page 24 of 32
8-Bit Interface (Master or Slave)
The BYTESWAP pin allows a glueless interface to an 8-bit bus.
As shown in Figure 38, when BYTESWAP is low, the LSB byte
is output on D[7:0] and the MSB is output on D[15:8]. When
BYTESWAP is high, the LSB and MSB bytes are swapped; the
LSB is output on D[15:8] and the MSB is output on D[7:0]. By
connecting BYTESWAP to an address line, the 16-bit data can
be read in two bytes on either D[15:8] or D[7:0]. This interface
can be used in both master and slave parallel reading modes.
CS
RD
BYTESWAP
PINS D[15:8]
PINS D[7:0]
HI-Z
HIGH BYTE
LOW BYTE
HIGH BYTE
HI-Z
t12
t13
06395-
038
Figure 38. 8-Bit and 16-Bit Parallel Interface
SERIAL INTERFACE
The AD7610 has a serial interface (SPI-compatible) multiplexed
on the data pins D[15:2]. The AD7610 is configured to use the
serial interface when SER/PAR is held high.
Data Interface
The AD7610 outputs 16 bits of data, MSB first, on the SDOUT pin.
This data is synchronized with the 16 clock pulses provided on
the SDCLK pin. The output data is valid on both the rising and
falling edge of the data clock.
Serial Configuration Interface
The AD7610 can be configured through the serial configuration
register only in serial mode as the serial configuration pins are
also multiplexed on the data pins D[15:12]. See the Hardware
Configuration section and Software Configuration section for
more information.
MASTER SERIAL INTERFACE
The pins multiplexed on D[10:2] and used for the master serial
interface are: DIVSCLK[0], DIVSCLK[1], EXT/INT, INVSYNC,
INVSCLK, RDC, SDOUT, SDCLK and SYNC.
Internal Clock (SER/PAR = High, EXT/INT = Low)
The AD7610 is configured to generate and provide the serial
data clock, SDCLK, when the EXT/INT pin is held low. The
AD7610 also generates a SYNC signal to indicate to the host
when the serial data is valid. The SDCLK, and the SYNC signals
can be inverted, if desired using the INVSCLK and INVSYNC
inputs, respectively. Depending on the input, RDC, the data can
be read during the following conversion or after each conver-
sion. Figure 39 and Figure 40 show detailed timing diagrams of
these two modes.
Read After Convert (RDC = Low, DIVSCLK[1:0] = [0 to 3])
Setting RDC = low, allows the read after conversion mode.
Since the AD7610 is limited to 250kSPS and the time between
conversions, t2 = 4s, this mode is the most recommended
serial mode. Unlike the other serial modes, the BUSY signal
returns low after the 16 data bits are pulsed out and not at the
end of the conversion phase, resulting in a longer BUSY width
(See Table 4 for BUSY timing specifications). The
DIVSCLK[1:0] inputs control the SDCLK period and SDOUT
data rate. As a result, the maximum throughput can only be
achieved in two of the DIVSCLK[1:0] settings. In this mode, the
AD7610 generates a discontinuous SDCLK however, a fixed
period and hosts supporting both SPI and serial ports can also
be used.
Read During Convert (RDC = High)
Setting RDC = high, allows the master read (previous conver-
sion result) during conversion mode. In this mode, the serial
clock and data toggle at appropriate instances, minimizing
potential feed through between digital activity and critical
conversion decisions. In this mode, the SDCLK period changes
since the LSBs require more time to settle and the SDCLK is
derived from the SAR conver-sion cycle. In this mode, the
AD7610 generates a discontinuous SDCLK of two different
periods and the host should use an SPI interface.
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