参数资料
型号: EVAL-AD7705EBZ
厂商: Analog Devices Inc
文件页数: 6/44页
文件大小: 0K
描述: BOARD EVALUATION FOR AD7705
标准包装: 1
ADC 的数量: 1
位数: 16
采样率(每秒): 500
数据接口: 串行
输入范围: 0 ~ 5.25 V
在以下条件下的电源(标准): 6.5mW @ 500SPS
工作温度: -40°C ~ 85°C
已用 IC / 零件: AD7705
已供物品: 板,CD
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AD7705/AD7706
Rev. C | Page 14 of 44
TYPICAL PERFORMANCE CHARACTERISTICS
READING NUMBER
32763
0
100
CODE
RE
AD
32764
32765
32766
32767
32768
32769
32770
32771
200
300
400
500
600
700
800
900
1000
VDD = 5V
VREF = 2.5V
GAIN = +128
50Hz UPDATE RATE
TA = 25°C
RMS NOISE = 600nV
01166-005
Figure 5. Noise @ Gain = +128 With 50 Hz Update Rate
FREQUENCY (MHz)
0.4
I DD
(mA)
VDD = 3V
TA = 25°C
1.2
1.0
0.8
0.6
0.4
0.2
0
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
BUFFERED MODE, GAIN = +128
UNBUFFERED MODE, GAIN = +1
UNBUFFERED MODE, GAIN = +128
BUFFERED MODE, GAIN = +1
01166-006
Figure 6. IDD vs. MCLK IN Frequency @ 3 V
GAIN
1
I DD
(
mA)
1.0
0.8
0.6
0.4
0.2
0
0.1
0.3
0.5
0.7
0.9
2
4
8
16
32
64
128
BUFFERED MODE
fCLK = 5MHz,
CLKDIV = 1
UNBUFFERED MODE
fCLK = 1MHz,
CLKDIV = 0
VDD = 3V
EXTERNAL MCLK
CLKDIS = 1
TA = 25°C
BUFFERED MODE
fCLK = 2.4576MHz, CLKDIV = 0
UNBUFFERED MODE
fCLK = 5MHz, CLKDIV = 1
UNBUFFERED MODE
fCLK = 2.84MHz, CLKDIV = 0
BUFFERED MODE
fCLK = 1MHz, CLKDIV = 0
01166-007
Figure 7. IDD vs. Gain and Clock Frequency @ 3 V
CODE
32764
OCCURRE
NCE
400
0
32765
32766
32767
32768
32769
32770
300
200
100
01166-008
Figure 8. Histogram of Data in Figure 5
FREQUENCY (MHz)
0.4
I DD
(mA)
VDD = 5V
TA = +25°C
1.2
1.0
0.8
0.6
0.4
0.2
0
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
BUFFERED MODE, GAIN = +128
UNBUFFERED MODE, GAIN = +1
UNBUFFERED MODE, GAIN = +128
BUFFERED MODE, GAIN = +1
01166-009
Figure 9. IDD vs. MCLK IN Frequency @ 5 V
GAIN
1
I DD
(mA)
VDD = 5V
EXTERNAL MCLK
CLKDIS = 1
TA = 25°C
1.2
0.8
0.6
0.4
0.2
0
1.0
2
4
8
16
32
64
128
BUFFERED MODE
fCLK = 5MHz,
CLKDIV = 1
BUFFERED MODE
fCLK = 1MHz, CLKDIV = 0
BUFFERED MODE
fCLK = 2.4576MHz, CLKDIV = 0
UNBUFFERED MODE
fCLK = 2.4576MHz, CLKDIV = 0
UNBUFFERED MODE
fCLK = 1MHz,
CLKDIV = 0
UNBUFFERED MODE
fCLK = 5MHz, CLKDIV = 1
01166-010
Figure 10. IDD vs. Gain and Clock Frequency @ 5 V
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