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参数资料
| 型号： | EVAL-AD7722CBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 14/24页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD7722CBZ |
| 标准包装： | 1 |
| ADC 的数量： | 1 |
| 位数： | 16 |
| 采样率（每秒）： | 220k |
| 数据接口： | 串行，并联 |
| 输入范围： | ±VREF/2 |
| 在以下条件下的电源（标准）： | 375mW @ 220kSPS |
| 工作温度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7722 |
| 已供物品： | 板，CD |
REV. B
AD7722
–21–
To interface the AD7722 to other DSPs, the master clock
frequency of the AD7722 can be reduced so that the SCO
frequency equals the maximum allowable frequency of the serial
clock input to the DSP. When the AD7722 is operated with a
lower CLKIN frequency (< 10 MHz), DSPs, such as the
TMS320C20/C25 and DSP56000/1, can be used.
Figures 26 to 28 show the interfaces between the AD7722 and
several DSPs. In all cases, the interface control pins, TSI, DOE,
SFMT, CFMT, SYNC, and FSI, can be permanently hardwired
together to either DGND or DVDD. Alternatively, SFMT or
CFMT can be tied either high or low to configure the serial data
interface for the particular format required by the DSP. The
frame synchronization signal, FSI, can be applied from the user’s
system control logic.
FSO
SDO
SCO
AD7722
RFS
DR
SCLK
ADSP-21xx
Figure 26. AD7722 to ADSP-21xx Interface
FSO
SDO
SCO
SC1
SRD
SCK
AD7722
DSP56001/2/3
Figure 27. AD7722 to DSP56000 Interface
FSO
SDO
SCO
FSR
DR
CLKR
AD7722
TMS320Cxx
Figure 28. AD7722 to TMS320C20/TMS320C25/
TMS320C50 Interface
CLKIN
RESET/SYNC
FSI
SCO
FSO (MASTER)
FSI (SLAVE)
DOE (MASTER AND SLAVE)
SDO (MASTER)
SDO (SLAVE)
t
1
t
14
NOTE 1
t
12
t
15
t
16
NOTE 1
t
11
t
16
t
15
D4
D3
D2
D1
D0
D15
D14
D1
D0
NOTE 1:
THE STATE OF FSI CANNOT BE CHANGED
4 CLKIN CYCLES BEFORE A FSO EDGE.
Figure 25. Timing for 2-Channel Multiplexed Operation
Grounding and Layout
The analog and digital power supplies to the AD7722 are indepen-
dent and separately pinned out to minimize coupling between
analog and digital sections within the device. The AD7722 should
be treated as an analog component and grounded and decoupled
to the analog ground plane. All the AD7722 ground pins should
be soldered directly to a ground plane to minimize series induc-
tance. All converter power pins should be decoupled to the analog
ground plane. To achieve the best decoupling, place surface-
mount capacitors as close as possible to the device, ideally right
up against the device pins.
The printed circuit board that houses the AD7722 should use
separate ground planes for the analog and digital interface
circuitry. All converter power pins should be decoupled to the
analog ground plane, and all interface logic circuit power pins
should be decoupled to the digital ground plane. This facili-
tates the use of ground planes, which can physically separate
sensitive analog components from the noisy digital system.
Digital and analog ground planes should only be joined in one
place and should not overlap to minimize capacitive coupling
between them.
Separate power supplies for AVDD and DVDD are also highly
desirable. The digital supply pin DVDD should be powered from
a separate analog supply, but if necessary DVDD may share its
power connection to AVDD (see the connection diagram in
Figure 29). The 10
resistor, in series with the DV
DD pin, is
required to dampen the effects of the fast switching currents into
the digital section of the AD7722. The ferrite is also recommended
to filter high frequency signals from corrupting the analog
power supply.
A minimum etch technique is generally best for ground planes
because it gives the best shielding. Noise can be minimized by
paying attention to the system layout and preventing different
signals from interfering with each other. High level analog signals
should be separated from low level analog signals, and both should
be kept away from digital signals. In waveform sampling and
reconstruction systems, the sampling clock (CLKIN) is as vulner-
able to noise as any analog signal. CLKIN should be isolated from
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