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参数资料
| 型号： | EVAL-AD7738EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 23/28页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD7738 |
| 标准包装： | 1 |
| ADC 的数量： | 1 |
| 位数： | 24 |
| 采样率（每秒）： | 15.4k |
| 数据接口： | 串行 |
| 输入范围： | ±2.5 V |
| 在以下条件下的电源（标准）： | 85mW @ 5V |
| 工作温度： | -40°C ~ 105°C |
| 已用 IC / 零件： | AD7738 |
| 已供物品： | 板 |
| 相关产品： | AD7738BRUZ-REEL7-ND - IC ADC 24BIT 8CH SIG-DEL 28TSSOP AD7738BRUZ-REEL-ND - IC ADC 24BIT 8CH SIG-DEL 28TSSOP AD7738BRUZ-ND - IC ADC 24BIT 8-CH 28-TSSOP AD7738BRU-REEL7-ND - IC ADC 24BIT 8CH SIG-DEL 28TSSOP AD7738BRU-ND - IC ADC 24BIT 8-CH 28-TSSOP |
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REV. 0
–4–
AD7738
TIMING SPECIFICATIONS1, 2, 3
(AVDD = 5 V
5%; DVDD = 2.7 V to 3.6 V or 5 V
5%; Input Logic 0 = 0 V, Logic 1 = DVDD unless otherwise noted.)
Parameter
Min
Typ
Max
Unit
Test Conditions/Comment
MASTER CLOCK RANGE
1
6.144
MHz
t1
50
ns
SYNC Pulsewidth
t2
500
ns
RESET Pulsewidth
READ OPERATION
t4
0ns
CS Falling Edge to SCLK Falling Edge Setup Time
t5
4
SCLK Falling Edge to Data Valid Delay
060
ns
DVDD of 4.75 V to 5.25 V
080
ns
DVDD of 2.7 V to 3.3 V
t5A
4, 5
CS Falling Edge to Data Valid Delay
060
ns
DVDD of 4.75 V to 5.25 V
080
ns
DVDD of 2.7 V to 3.3 V
t6
50
ns
SCLK High Pulsewidth
t7
50
ns
SCLK Low Pulsewidth
t8
0ns
CS Rising Edge after SCLK Rising Edge Hold Time
t9
6
10
80
ns
Bus Relinquish Time after SCLK Rising Edge
WRITE OPERATION
t11
0ns
CS Falling Edge to SCLK Falling Edge Setup
t12
30
ns
Data Valid to SCLK Rising Edge Setup Time
t13
25
ns
Data Valid after SCLK Rising Edge Hold Time
t14
50
ns
SCLK High Pulsewidth
t15
50
ns
SCLK Low Pulsewidth
t16
0ns
CS Rising Edge after SCLK Rising Edge Hold Time
NOTES
1Sample tested during initial release to ensure compliance.
2All input signals are specified with tr = tf = 5 ns (10% to 90% of DV
DD) and timed from a voltage level of 1.6 V.
3See Figures 1 and 2.
4These numbers are measured with the load circuit of Figure 3 and defined as the time required for the output to cross the V
OL or VOH limits.
5This specification is relevant only if CS goes low while SCLK is low.
6These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 3.
The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing
characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances.
Specifications are subject to change without notice.
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相关代理商/技术参数 |
参数描述 |
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| EVAL-AD7739EB | 制造商:Analog Devices 功能描述:EVALUATION BOARD I.C. - Bulk |
| EVAL-AD7739EBZ | 功能描述:BOARD EVAL FOR AD7739 RoHS:是 类别:编程器，开发系统 >> 评估板 - 模数转换器 (ADC) 系列:- 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:- ADC 的数量:1 位数:12 采样率（每秒）:94.4k 数据接口:USB 输入范围:±VREF/2 在以下条件下的电源（标准）:- 工作温度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，软件 |
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| EVAL-AD7741-42EBZ | 制造商:AD 制造商全称:Analog Devices 功能描述:Single and Multichannel, Synchronous Voltage-to-Frequency Converters |
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