AD7993/AD7994
Rev. 0 | Page 15 of 32
CIRCUIT INFORMATION
The AD7993/AD7994 are low power, 10- and 12-bit, single-
supply, 4-channel A/D converters, respectively. The parts can
be operated from a 2.7 V to 5.5 V supply.
The AD7993/AD7994 provide the user with a 4-channel
multiplexer, an on-chip track-and-hold, an A/D converter, an
on-chip oscillator, internal data registers, and an I2C-compatible
serial interface, all housed in a 16-lead TSSOP package that
offers the user considerable space-saving advantages over
alternative solutions. The AD7993/AD7994 require an external
reference in the range of 1.2 V to VDD.
The AD7993/AD7994 normally remain in a power-down state
while not converting. When supplies are first applied, the parts
come up in a power-down state. Power-up is initiated prior to
a conversion, and the device returns to shutdown upon com-
pletion of the conversion. Conversions can be initiated on the
AD7993/AD7994 by pulsing the CONVST signal, using an
automatic cycle interval mode, or using a command mode
where wake-up and a conversion occurs during a write address
version is complete, the AD7993/AD7994 again enter shutdown
mode. This automatic shut-down feature allows power saving
between conversions. Any read or write operations across the
I2C interface can occur while the devices are in shutdown.
CONVERTER OPERATION
The AD7993/AD7994 are successive approximation analog-to-
acquisition and conversion phase, respectively.
Figure 18 shows
an ADC during the acquisition phase. SW2 is closed and SW1
is in Position A. The comparator is held in a balanced condition
and the sampling capacitor acquires the signal on VINx.
CAPACITIVE
DAC
VIN
COMPARATOR
CONTROL
LOGIC
SW1
A
B
SW2
AGND
03472-0-018
Figure 18. ADC Acquisition Phase
When the ADC starts a conversion, as shown in
Figure 19, SW2
opens and SW1 moves to Position B, causing the comparator to
become unbalanced. The input is disconnected once the con-
version begins. The control logic and the capacitive DAC are
used to add and subtract fixed amounts of charge from the
sampling capacitor to bring the comparator back into a
balanced condition. When the comparator is rebalanced, the
conversion is complete. The control logic generates the ADC
VIN
COMPARATOR
CONTROL
LOGIC
SW1
A
B
SW2
AGND
CAPACITIVE
DAC
03472-0-019
Figure 19. ADC Conversion Phase
ADC Transfer Function
The output coding of the AD7993/AD7994 is straight binary.
The designed code transitions occur at successive integer LSB
values—that is, 1 LSB, 2 LSB, and so on. The LSB size is
REFIN/1024 for the AD7993 and REFIN/4096 for the AD7994.
AD7993/AD7994.
000...000
ADC
CODE
ANALOG INPUT
0V TO REFIN
111...111
000...001
000...010
111...110
111...000
011...111
AGND + 1LSB
+REFIN – 1LSB
AD7994 1LSB = REFIN/4096
AD7993 1LSB = REFIN/1024
03472-0-020
Figure 20. AD7993/AD7994 Transfer Characteristic