参数资料
| 型号： | EVAL-AD9830EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 3/7页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION AD9830 |
| 产品培训模块： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 标准包装： | 1 |
| 主要目的： | 计时，直接数字合成（DDS） |
| 已用 IC / 零件： | AD9830 |
| 已供物品： | 板 |
| 相关产品： | AD9830ASTZ-REEL-ND - IC DDS 10BIT 50MHZ CMOS 48TQFP AD9830ASTZ-ND - IC DDS 10BIT 50MHZ CMOS 48-TQFP |
Preliminary Technical Data
SET-UP CONDITIONS
Care should be taken before applying power and signals to the
evaluation board to ensure that all link positions are as per the
required operating mode. Table 1 shows the position in which
AD7002
EVAL-AD9830EB
36-Way Connector Pin Description
DGND Digital Ground. These lines are connected
to the digital ground plane on the evaluation
board.
all the links are set when the evaluation board is sent out.
Table 1. Initial Link and Switch Positions
DB0 - DB7
Data Bit 0 to Data Bit 7. Data transfers
from the PC are 8 bits wide. Therefore, the
16 bit word is split into two 8 bit words.
For each write operation, there are 3
transfers of data from the PC: the 8 MSBs
Link No.
LK1
Function
LK1 is arranged so that PSEL1 is tied to
SW.
of the 16 bit word, the 8 LSBs of the 16 bit
word and the address data to bits A0, A1
and A2. The AD9830 accepts CMOS logic.
LK2
LK3
LK4
LK5
SW
LK2 is arranged so that PSEL0 is tied to
SW.
LK3 is arranged so that FSELECT is tied to
SW.
LK4 is connected so that SLEEP is tied to
DVDD and, hence, the AD9830 is powered
up.
REFOUT is tied to REFIN.
All the SW switches are arranged so that
DVDD is selected.
LOAD
LATCH
WR
When the 8 MSBs of the 16 bit word are
written to the evaluation board from the PC,
the word is held in a latch, a 74HC574 latch.
This latch latches in the data on the rising
edge of the CK signal. The LOAD signal
provides this rising edge.
The 8 LSBs of the 16 bit word are held in
the latch U3. The rising CK edge to this
part is provided by LATCH.
Write. This is an active low logic input
which is used to write the digital data to the
AD9830. When the address bits A0, A1 and
A2 are being written to, the WR signal is
EVALUATION BOARD INTERFACING
Interfacing to the evaluation board is via a 36-way centronics
female connector, J1. The pinout for the J1 connector is
shown in Figure 1 and its pin designations are given in Table
generated also. On the rising edge of WR ,
the AD9830 reads in the 16 bit word from
the 74HC574 latches along with the address
values.
2.
36
1
19
18
RESET
Reset. When RESET is taken low, the
AD9830 is reset. On reset, the phase
accumulator is reset to zero.
Figure1. Pin Configuration for the 36-Way Connector, J1.
-3-
REV 0
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| EVAL-AD9831EB | 制造商:Analog Devices 功能描述: |
| EVAL-AD9831EBZ | 功能描述:BOARD EVALUATION AD9831 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:- 主要目的:电信，线路接口单元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要属性:T1/J1/E1 LIU 次要属性:- 已供物品:板，电源，线缆，CD 其它名称:82EBV2081 |
| EVAL-AD9832EB | 制造商:Analog Devices 功能描述:EVALUATION BOARD I.C. - Bulk 制造商:Analog Devices 功能描述:AD9832 EVAL BOARD |
| EVAL-AD9832SDZ | 功能描述:BOARD EVAL FOR AD9832 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:* 标准包装:1 系列:- 主要目的:电信，线路接口单元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要属性:T1/J1/E1 LIU 次要属性:- 已供物品:板，电源，线缆，CD 其它名称:82EBV2081 |
| EVAL-AD9833EB | 制造商:AD 制造商全称:Analog Devices 功能描述:+2.5 V to +5.5 V, 25 MHz Low Power CMOS Complete DDS |
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