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| 型号： | EVAL-AD9835EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 7/28页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD9835 |
| 产品培训模块： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 标准包装： | 1 |
| 主要目的： | 计时，直接数字合成（DDS） |
| 已用 IC / 零件： | AD9835 |
| 已供物品： | 板 |
| 相关产品： | AD9835BRUZ-REEL7-ND - IC DDS 10BIT 50MHZ 16-TSSOP AD9835BRUZ-REEL-ND - IC DDS 10BIT 50MHZ 16-TSSOP AD9835BRUZ-ND - IC DDS 10BIT 50MHZ 16-TSSOP AD9835BRU-REEL7-ND - IC DDS 10BIT 50MHZ 16-TSSOP AD9835BRU-ND - IC DDS DAC 10BIT 50MHZ 16-TSSOP |
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Data Sheet
AD9835
Rev. A | Page 15 of 28
FUNCTIONAL DESCRIPTION
SERIAL INTERFACE
The AD9835 has a serial interface, with 16 bits loaded during
each write cycle. SCLK, SDATA, and FSYNC are used to load
the word into the AD9835.
When FSYNC is taken low, the AD9835 is informed that a word
is being written to the device. The first bit is read into the device
on the next SCLK falling edge with the remaining bits being read
into the device on the subsequent SCLK falling edges. FSYNC
frames the 16 bits; therefore, when 16 SCLK falling edges have
occurred, FSYNC should be taken high again. The SCLK can be
continuous, or alternatively, the SCLK can idle high or low between
write operations. When writing to a frequency/phase register,
the first four bits identify whether a frequency or phase register
is being written to, the next four bits contain the address of the
destination register, while the 8 LSBs contain the data.
Table 5 shows the data structure for a 16-bit write to the
For examples on programming the AD9835, see the AN-621
and AN-1108 application notes at www.analog.com.
Table 5. Writing to the AD9835 Data Registers
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
C3
C2
C1
C0
A3
A2
A1
A0
MSB
X1
X1
LSB
1 X = don’t care.
Table 6. Commands
C3
C2
C1
C0
Command
0
Write 16 phase bits (present 8 bits + 8 bits
in the defer register) to selected PHASEx REG.
0
1
Write 8 phase bits to the defer register.
0
1
0
Write 16 frequency bits (present 8 bits +
8 bits in the defer register) to selected the
FREQx REG.
0
1
Write 8 frequency bits to the defer register.
0
1
0
Bit D9 (PSEL0) and Bit D10 (PSEL1) are used
to select the PHASEx REG when SELSRC = 1.
When SELSRC = 0, the PHASEx REG is
selected using the PSEL0 and PSEL1 pins.
0
1
0
1
Bit D11 is used to select the FREQx REG
when SELSRC = 1. When SELSRC = 0, the
FREQx REG is selected using the FSELECT pin.
0
1
0
To control the PSEL0, PSEL1, and FSELECT
bits using only one write, this command is
used. Bit D9 and Bit D10 are used to select
the PHASEx REG, and Bit 11 is used to select
the FREQx REG when SELSRC = 1. When
SELSRC = 0, the PHASEx REG is selected
using the PSEL0 and PSEL1 pins and the
FREQx REG is selected using the FSELECT pin.
0
1
Reserved. It configures the AD9835 for
test purposes.
Table 7. Addressing the Registers
A3
A2
A1
A0
Destination Register
0
FREQ0 REG 8 L LSBs
0
1
FREQ0 REG 8 H LSBs
0
1
0
FREQ0 REG 8 L MSBs
0
1
FREQ0 REG 8 H MSBs
0
1
0
FREQ1 REG 8 L LSBs
0
1
0
1
FREQ1 REG 8 H LSBs
0
1
0
FREQ1 REG 8 L MSBs
0
1
FREQ1 REG 8 H MSBs
1
0
PHASE0 REG 8 LSBs
1
0
1
PHASE0 REG 8 MSBs
1
0
1
0
PHASE1 REG 8 LSBs
1
0
1
PHASE1 REG 8 MSBs
1
0
PHASE2 REG 8 LSBs
1
0
1
PHASE2 REG 8 MSBs
1
0
PHASE3 REG 8 LSBs
1
PHASE3 REG 8 MSBs
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