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参数资料
| 型号： | EVAL-ADCMP562BRQZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 3/16页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION ADCMP562BRQZ |
| 标准包装： | 1 |
| 主要目的： | 接口，比较器 |
| 已用 IC / 零件： | ADCMP562 |
| 已供物品： | 板 |
| 相关产品： | ADCMP562BRQ-ND - IC COMPARATOR PECL DUAL 20QSOP ADCMP562BRQZ-ND - IC COMPARATOR PECL DUAL 20-QSOP |
ADCMP561/ADCMP562
Rev. A | Page 11 of 16
APPLICATION INFORMATION
The ADCMP561/ADCMP562 comparators are very high speed
devices. Consequently, high speed design techniques must be
employed to achieve the best performance. The most critical
aspect of any ADCMP561/ADCMP562 design is the use of a
low impedance ground plane. A ground plane, as part of a
multilayer board, is recommended for proper high speed
performance. Using a continuous conductive plane over the
surface of the circuit board can create this, allowing breaks in
the plane only for necessary signal paths. The ground plane
provides a low inductance ground, eliminating any potential
differences at different ground points throughout the circuit
board caused by ground bounce. A proper ground plane also
minimizes the effects of stray capacitance on the circuit board.
It is also important to provide bypass capacitors for the power
supply in a high speed application. A 1 F electrolytic bypass
capacitor should be placed within 0.5 inches of each power
supply pin to ground. These capacitors reduce any potential
voltage ripples from the power supply. In addition, a 10 nF
ceramic capacitor should be placed as close as possible from the
power supply pins on the ADCMP561/ADCMP562 to ground.
These capacitors act as a charge reservoir for the device during
high frequency switching.
The LATCH ENABLE input is active low (latched). If the
latching function is not used, the LATCH ENABLE input may
be left open or may be attached to VDD (VDD is a PECL logic
high). The complementary input, LATCH ENABLE, may be left
open or may be tied to VDD 2.0 V. Leaving the latch inputs
unconnected or providing the proper voltages disables the
latching function.
Occasionally, one of the two comparator stages within the
ADCMP561/ADCMP562 is not used. The inputs of the unused
comparator should not be allowed to float. The high internal
gain may cause the output to oscillate (possibly affecting the
comparator that is being used) unless the output is forced into a
fixed state. This is easily accomplished by ensuring that the two
inputs are at least one diode drop apart, while also appropriately
connecting the LATCH ENABLE and LATCH ENABLE inputs
as described previously.
The best performance is achieved with the use of proper PECL
terminations. The open emitter outputs of the ADCMP561/
ADCMP562 are designed to be terminated through 50
resistors to VDD 2.0 V, or any other equivalent PECL termin-
ation. If high speed PECL signals must be routed more than a
centimeter, microstrip or stripline techniques may be required
to ensure proper transition times and prevent output ringing.
CLOCK TIMING RECOVERY
Comparators are often used in digital systems to recover clock
timing signals. High speed square waves transmitted over a
distance, even tens of centimeters, can become distorted due to
stray capacitance and inductance. Poor layout or improper
termination can also cause reflections on the transmission line,
further distorting the signal waveform. A high speed
comparator can be used to recover the distorted waveform
while maintaining a minimum of delay.
OPTIMIZING HIGH SPEED PERFORMANCE
As with any high speed comparator amplifier, proper design and
layout techniques should be used to ensure optimal perform-
ance from the ADCMP561/ADCMP562. The performance
limits of high speed circuitry can be a result of stray capaci-
tance, improper ground impedance, or other layout issues.
Minimizing resistance from source to the input is an important
consideration in maximizing the high speed operation of the
ADCMP561/ADCMP562. Source resistance in combination
with equivalent input capacitance could cause a lagged response
at the input, thus delaying the output. The input capacitance of
the ADCMP561/ADCMP562, in combination with stray
capacitance from an input pin to ground, could result in several
picofarads of equivalent capacitance. A combination of 3 k
source resistance and 5 pF of input capacitance yields a time
constant of 15 ns, which is significantly slower than the 750 ps
capability of the ADCMP561/ADCMP562. Source impedances
should be significantly less than 100 for best performance.
Sockets should be avoided due to stray capacitance and induc-
tance. If proper high speed techniques are used, the devices
should be free from oscillation when the comparator input
signal passes through the switching threshold.
COMPARATOR PROPAGATION DELAY
DISPERSION
The ADCMP561/ADCMP562 have been specifically designed
to reduce propagation delay dispersion over an input overdrive
range of 100 mV to 1.5 V. Propagation delay overdrive
dispersion is the change in propagation delay that results from a
change in the degree of overdrive (how far the switching point
is exceeded by the input). The overall result is a higher degree of
timing accuracy because the ADCMP561/ADCMP562 are far
less sensitive to input variations than most comparator designs.
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相关代理商/技术参数 |
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|---|---|
| EVAL-ADCMP563BRQ | 制造商:Analog Devices 功能描述:EVAL BD FOR THE DUAL HS PECL COMPARATOR - Bulk |
| EVAL-ADCMP563BRQZ | 功能描述:BOARD EVALUATION ADCMP563BRQZ RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:- 主要目的:电信，线路接口单元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要属性:T1/J1/E1 LIU 次要属性:- 已供物品:板，电源，线缆，CD 其它名称:82EBV2081 |
| EVAL-ADCMP564BRQ | 制造商:AD 制造商全称:Analog Devices 功能描述:Dual, High Speed ECL Comparators |
| EVAL-ADCMP564BRQZ | 功能描述:BOARD EVALUATION ADCMP564BRQZ RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:- 主要目的:电信，线路接口单元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要属性:T1/J1/E1 LIU 次要属性:- 已供物品:板，电源，线缆，CD 其它名称:82EBV2081 |
| EVAL-ADCMP565BPZ | 功能描述:BOARD EVALUATION ADCMP565BPZ RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:- 主要目的:电信，线路接口单元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要属性:T1/J1/E1 LIU 次要属性:- 已供物品:板，电源，线缆，CD 其它名称:82EBV2081 |
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