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| 型号： | EVAL-ADCMP604BKSZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 14/16页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADCMP604 SC70-6 |
| 标准包装： | 1 |
| 主要目的： | 比较器，单路 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADCMP604 |
| 主要属性： | LVDS 兼容输出 |
| 已供物品： | 板 |
ADCMP604/ADCMP605
Rev. A | Page 7 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADCMP604
TOP VIEW
(Not to Scale)
Q 1
Q
6
VEE 2
VCCI/VCCO
5
VP 3
VN
4
05
916
-00
2
Figure 3. ADCMP604 Pin Configuration
Table 5. ADCMP604 Pin Function Descriptions (6-Lead SC70)
Pin No.
Mnemonic
Description
1
Q
Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, VP, is greater than the
analog voltage at the inverting input, VN.
2
VEE
Negative Supply Voltage.
3
VP
Noninverting Analog Input.
4
VN
Inverting Analog Input.
5
VCCI/VCCO
Input Section Supply/Output Section Supply. VCCI and VCCO are shared pin.
6
Q
Inverting Output. Q is at logic low if the analog voltage at the noninverting input, VP, is greater than the analog
voltage at the inverting input, VN.
PIN 1
INDICATOR
TOP VIEW
(Not to Scale)
ADCMP605
VCCO 1
VCCI 2
VEE 3
V
P
4
V
EE
5
V
N
6
9 VEE
8 LE/HYS
7 SDN
12
Q
11
V
EE
10
Q
05
91
6-
00
3
Figure 4. ADCMP605 Pin Configuration
Table 6. ADCMP605 Pin Function Descriptions (12-Lead LFCSP_VQ)
Pin No.
Mnemonic
Description
1
VCCO
Output Section Supply.
2
VCCI
Input Section Supply.
3, 5, 9, 11
VEE
Negative Supply Voltages.
4
VP
Noninverting Analog Input.
6
VN
Inverting Analog Input.
7
SDN
Shutdown. Drive this pin low to shut down the device.
8
LE/HYS
Latch/Hysteresis Control. Bias with resistor or current for hysteresis; drive low to latch.
10
Q
Inverting Output. Q is at Logic low if the analog voltage at the noninverting input, VP, is greater than
the analog voltage at the inverting input, VN, if the comparator is in compare mode.
12
Q
Noninverting Output. Q is at Logic high if the analog voltage at the noninverting input, VP, is greater
than the analog voltage at the inverting input, VN, if the comparator is in compare mode.
Heat Sink Paddle
VEE
The metallic back surface of the package is electrically connected to VEE. It can be left floating
because Pin 3, Pin 5, Pin 9, and Pin 11 provide adequate electrical connection. It can also be
soldered to the application board if improved thermal and/or mechanical stability is desired.
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