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参数资料
| 型号： | EVAL-ADCMP605BCPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 4/16页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADCMP605 |
| 标准包装： | 1 |
| 主要目的： | 比较器，单路 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADCMP605 |
| 主要属性： | LVDS 兼容输出 |
| 已供物品： | 板 |
ADCMP604/ADCMP605
Rev. A | Page 12 of 16
The hysteresis control pin appears as a 1.25 V bias voltage
seen through a series resistance of 70 kΩ ± 20% throughout the
hysteresis control range. The advantages of applying hysteresis
in this manner are improved accuracy, improved stability, reduced
component count, and maximum versatility. An external bypass
capacitor is not recommended on the HYS pin because it would
likely degrade the jitter performance of the device and impair the
latch function. As described in the Using/Disabling the Latch
Feature section, hysteresis control need not compromise the
latch function.
0
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500
HYSTERESIS RESISTOR (k)
H
Y
ST
E
R
ES
IS
(
m
V
)
VCC = 2.5V
VCC = 5.5V
05
91
6-
0
26
Figure 20. Hysteresis vs. RHYS Control Resistor
CROSSOVER BIAS POINTS
Rail-to-rail inputs of this type, in both op amps and comparators,
have a dual front-end design. Certain devices are active near
the VCCI rail and others are active near the VEE rail. At some pre-
determined point in the common-mode range, a crossover
occurs. At this point, normally VCCI/2, the direction of the bias
current reverses and there are changes in measured offset
voltages and currents.
MINIMUM INPUT SLEW RATE REQUIREMENT
With the rated load capacitance and normal good PCB design
practice, as discussed in the Optimizing Performance section,
these comparators should be stable at any input slew rate with
no hysteresis. Broadband noise from the input stage is observed
in place of the violent chattering seen with most other high
speed comparators. With additional capacitive loading or poor
bypassing, oscillation is observed. This oscillation is due to the
high gain bandwidth of the comparator in combination with
feedback parasitics in the package and PCB. In many applications,
chattering is not harmful.
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