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| 型号： | EVAL-ADG2128EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 13/28页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADG2128 |
| 产品变化通告： | Interface Change Notice 12/Apr/2010 |
| 标准包装： | 1 |
| 主要目的： | 接口，交叉点开关/多路复用器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADG2128 |
| 主要属性： | 8 x 12 模拟多路复用器，8 ~ 12V 或 +/- 5V |
| 次要属性： | 图形用户界面 |
| 已供物品： | 板 |
| 相关产品： | ADG2128BCPZ-REEL7TR-ND - IC CROSSPOINT SWIT 8X12 32LFCSP ADG2128BCPZ-REEL-ND - IC CROSSPOINT SWIT 8X12 32LFCSP ADG2128YCPZ-HS-RL7DKR-ND - IC CROSSPOINT SWIT 8X12 32LFCSP ADG2128BCPZ-HS-RL7DKR-ND - IC CROSSPOINT SWIT 8X12 32LFCSP ADG2128YCPZ-HS-RL7CT-ND - IC CROSSPOINT SWIT 8X12 32LFCSP ADG2128BCPZ-HS-RL7CT-ND - IC CROSSPOINT SWIT 8X12 32LFCSP ADG2128YCPZ-HS-RL7TR-ND - IC CROSSPOINT SWIT 8X12 32LFCSP ADG2128BCPZ-HS-RL7TR-ND - IC CROSSPOINT SWIT 8X12 32LFCSP ADG2128YCPZ-REEL7TR-ND - IC CROSSPOINT SWIT 8X12 32LFCSP ADG2128YCPZ-REEL-ND - IC CROSSPOINT SWIT 8X12 32LFCSP |
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ADG2128
Data Sheet
Rev. D | Page 20 of 28
WRITING TO THE ADG2128
INPUT SHIFT REGISTER
The input shift register is 24 bits wide. A 3-byte write is necessary when writing to this register and is done under the control of the serial
clock input, SCL. The contents of the three bytes of the input shift register are shown in Figure 33 and described in Table 6.
05464-
004
X
LDSW
DB0 (LSB)
DB7 (MSB)
DATA BITS
DATA AX3 AX2
AX1
AX0
AY2
AY1 AY0
DB8 (LSB)
DB15 (MSB)
DATA BITS
1
0
A2
A1
A0
R/W
DB16 (LSB)
DEVICE ADDRESS
DB23 (MSB)
Figure 33. Data-Words
Table 6. Input Shift Register Bit Function Descriptions
Bit
Mnemonic
Description
DB23 to DB17
1110xxx
The MSBs of the ADG2128 are set to 1110. The LSBs of the address byte are set by the state
of the three address pins, Pin A0, Pin A1, and Pin A2.
DB16
R/W
Controls whether the ADG2128 slave device is read from or written to.
If R/W = 1, the ADG2128 is being read from.
If R/W = 0, the ADG2128 is being written to.
DB15
Data
Controls whether the switch is to be open (off) or closed (on).
If Data = 0, the switch is open/off.
If Data = 1, the switch is closed/on.
DB14 to DB11
AX3 to AX0
Controls I/Os X0 to X11. See Table 7 for the decode truth table.
DB10 to DB8
AY2 to AY0
Controls I/Os Y0 to Y7. See Table 7 for the decode truth table.
DB7 to DB1
X
Don’t care.
DB0
LDSW
This bit is useful when a number of switches need to be simultaneously updated.
If LDSW = 1, the switch position changes after the new word is read.
If LDSW = 0, the input data is latched, but the switch position is not changed.
As shown in Table 6, Bit DB11 to Bit DB14 control the X input/output lines, while Bit DB8 to Bit DB10 control the Y input/output lines.
Table 7 shows the truth table for these bits. Note the full coding sequence is written out for Channel Y0, and Channel Y1 to Channel Y7
follow a similar pattern. Note also that the RESET pin must be high when writing to the device.
Table 7. Address Decode Truth Table
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
Switch Configuration
DATA
AX3
AX2
AX1
AX0
AY2
AY1
AY0
1
0
X0 to Y0 (on)
0
X0 to Y0 (off)
1
0
1
0
X1 to Y0 (on)
0
1
0
X1 to Y0 (off)
1
0
1
0
X2 to Y0 (on)
0
1
0
X2 to Y0 (off)
1
0
1
0
X3 to Y0 (on)
0
1
0
X3 to Y0 (off)
1
0
1
0
X4 to Y0 (on)
0
1
0
X4 to Y0 (off)
1
0
1
0
1
0
X5 to Y0 (on)
0
1
0
1
0
X5 to Y0 (off)
X
0
1
0
Reserved
X
0
1
0
Reserved
1
0
X6 to Y0 (on)
0
1
0
X6 to Y0 (off)
1
0
1
0
X7 to Y0 (on)
0
1
0
1
0
X7 to Y0 (off)
1
0
1
0
X8 to Y0 (on)
0
1
0
1
0
X8 to Y0 (off)
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