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参数资料
| 型号： | EVAL-ADM1069LQEBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 26/32页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADM1069LQ |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电源监控器/跟踪器/序列发生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADM1069 |
| 主要属性： | 10 通道监控器 / 序列发生器，6 个电压输出 DAC |
| 次要属性： | 通过 SMBus（通过 USB）实现的可编程 GUI |
| 已供物品： | 2 个板，线缆，CD |
| 相关产品： | ADM1069ASTZ-REEL7TR-ND - IC SEQUENCER/SUPERVISOR 32LQFP ADM1069ASTZ-REEL-ND - IC SEQUENCER/SUPERVISOR 32LQFP ADM1069ASTZ-ND - IC SUPERVISOR/SEQUENCER 32-LQFP |
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ADM1069
The device also has several identification registers (read-only)
that can be read across the SMBus. Table 12 lists these registers
with their values and functions.
Table 12. Identification Register Values and Functions
All other devices on the bus remain idle while the selected device
waits for data to be read from or written to it. If the R/W bit is a 0,
the master writes to the slave device. If the R/W bit is a 1, the
master reads from the slave device.
Name
MANID
REVID
MARK1
MARK2
Address
0xF4
0xF5
0xF6
0xF7
Value
0x41
0x02
0x00
0x00
Function
Manufacturer ID for Analog Devices
Silicon revision
Software brand
Software brand
Step 2
Data is sent over the serial bus in sequences of nine clock pulses:
eight bits of data followed by an acknowledge bit from the slave
device. Data transitions on the data line must occur during the
low period of the clock signal and remain stable during the high
General SMBus Timing
general read and write operations using the SMBus. The SMBus
specification defines specific conditions for different types of
read and write operations, which are discussed in the Write
Operations and Read Operations sections.
The general SMBus protocol operates as follows:
Step 1
The master initiates data transfer by establishing a start condition,
defined as a high-to-low transition on the serial data line SDA,
while the serial clock line SCL remains high. This indicates that
a data stream follows. All slave peripherals connected to the serial
bus respond to the start condition and shift in the next eight bits,
consisting of a 7-bit slave address (MSB first) plus an R/W bit.
This bit determines the direction of the data transfer, that is,
whether data is written to or read from the slave device (0 = write,
1 = read).
The peripheral whose address corresponds to the transmitted
address responds by pulling the data line low during the low period
before the ninth clock pulse, known as the acknowledge bit, and
by holding it low during the high period of this clock pulse.
period because a low-to-high transition when the clock is high
could be interpreted as a stop signal. If the operation is a write
operation, the first data byte after the slave address is a command
byte. This command byte tells the slave device what to expect next.
It may be an instruction telling the slave device to expect a block
write, or it may be a register address that tells the slave where
subsequent data is to be written. Because data can flow in only
one direction, as defined by the R/W bit, sending a command
to a slave device during a read operation is not possible. Before
a read operation, it may be necessary to perform a write operation
to tell the slave what sort of read operation to expect and/or the
address from which data is to be read.
Step 3
When all data bytes have been read or written, stop conditions
are established. In write mode, the master pulls the data line high
during the 10th clock pulse to assert a stop condition. In read
mode, the master device releases the SDA line during the low
period before the ninth clock pulse, but the slave device does not
pull it low. This is known as a no acknowledge. The master then
takes the data line low during the low period before the 10th clock
pulse and then high during the 10th clock pulse to assert a stop
condition.
1
9
1
9
SCL
SDA
1
0
0
1
1
A1
A0
R/W
D7
D6
D5
D4
D3
D2
D1
D0
START BY
MASTER
FRAME 1
SLAVE ADDRESS
ACK. BY
SLAVE
FRAME 2
COMMAND CODE
ACK. BY
SLAVE
SCL
(CONTINUED)
1
9
1
9
SDA
(CONTINUED)
D7
D6
D5
D4 D3 D2
FRAME 3
DATA BYTE
D1
D0
ACK. BY
SLAVE
D7
D6
D5
D4 D3 D2
FRAME N
DATA BYTE
D1
D0
ACK. BY
SLAVE
STOP
BY
MASTER
Figure 36. General SMBus Write Timing Diagram
Rev. C | Page 26 of 32
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