参数资料
| 型号： | EVAL-ADM1172EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 5/16页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADM1172 |
| 产品培训模块： | Hot Swap Design |
| 标准包装： | 1 |
| 主要目的： | 电源管理，热交换控制器 |
| 已用 IC / 零件： | ADM1172 |
| 已供物品： | 板 |
| 相关产品： | ADM1172-2AUJZ-RL7DKR-ND - IC CTRLR HOTSWAP 16.5V TSOT-23-8 ADM1172-1AUJZ-RL7DKR-ND - IC CTRLR HOTSWAP 16.5V TSOT-23-8 ADM1172-2AUJZ-RL7CT-ND - IC CTRLR HOTSWAP 16.5V TSOT-23-8 ADM1172-1AUJZ-RL7CT-ND - IC CTRLR HOTSWAP 16.5V TSOT-23-8 ADM1172-2AUJZ-RL7TR-ND - IC CTRLR HOTSWAP 16.5V TSOT-23-8 ADM1172-1AUJZ-RL7TR-ND - IC CTRLR HOTSWAP 16.5V TSOT-23-8 |
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
ADM1172-1AUJ
ADM1172-2AUJ
ADM1172
TIMER 1
8
V CC
TIMER 1
8
V CC
GND 2
TOP VIEW
7
SENSE
GND 2
TOP VIEW
7
SENSE
PFO 3 (Not to Scale) 6 PFI
PFO 3 (Not to Scale) 6 PFI
ON 4
5
GATE
ON-CLR 4
5
GATE
Figure 2. Pin Configuration, 1AUJ Model
Table 4. Pin Function Descriptions
Figure 3. Pin Configuration, 2AUJ Model
Pin No.
1
2
3
4
5
6
7
8
Mnemonic
TIMER
GND
PFO
ON (ON-CLR)
GATE
PFI
SENSE
V CC
Description
Timer Input Pin. The initial and circuit breaker timing cycles are set by this external capacitor. The initial timing
delay is 272.9 ms/μF, and 21.7 ms/μF for a circuit breaker delay. When the TIMER pin is pulled beyond the upper
threshold, the GATE turns off.
Chip Ground Pin.
Power-Fail Comparator Output. Digital output from the power-fail comparator.
Input Pin. The ON (ON-CLR) pin is an input to a comparator that has a low-to-high threshold of 1.3 V with 80 mV
hysteresis and a glitch filter. The ADM1172 is reset when the ON (ON-CLR) pin is low. When the ON (ON-CLR) pin is
high, the ADM1172 is enabled. A rising edge on this pin has the added function of clearing a fault and restarting
Gate Output Pin. An internal charge pump provides a 12 μA pull-up current to drive the gate of an N-channel
MOSFET. In an overcurrent condition, the ADM1172 controls the external FET to maintain a constant load
current.
Power-Fail Comparator Input. Comparator threshold = 0.6 V.
Current Limit Sense Input Pin. The current limit is set via a sense resistor between the V CC and SENSE pins. In an
overcurrent condition, the gate of the FET is controlled to maintain the SENSE voltage at 50 mV. When this limit is
reached, the TIMER circuit breaker mode is activated. The circuit breaker limit can be disabled by connecting the
V CC pin and SENSE pin together.
Positive Supply Input Pin. The ADM1172 operates between 2.7 V to 16.5 V. An undervoltage lockout (UVLO)
circuit with a glitch filter resets the ADM1172 when the supply voltage drops below the specified UVLO limit.
Rev. A | Page 5 of 16
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