参数资料
| 型号： | EVAL-ADM1276EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 34/48页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADM1276 |
| 标准包装： | 1 |
| 系列： | * |
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ADM1276
Data Sheet
More than one device may have an active SMBAlert signal and
attempt to communicate with the host. In this case, the device
with the lowest address dominates the bus and succeeds in
transmitting its address to the host. The device that succeeds
disables its SMBus alert signal. If the host sees that the SMBus
alert signal is still low, it continues to read addresses until all
devices that need to talk to it have successfully transmitted their
addresses.
EXAMPLE USE OF SMBus ALERT RESPONSE
ADDRESS
The full sequence of steps that occurs when an SMBAlert is
generated and cleared is as follows:
1. A fault or warning is enabled using the ALERT2_CONFIG
command, and the corresponding status bit for the fault or
warning changes from 0 to 1, indicating that the fault or
warning has just become active.
2. The GPO2/ALERT2 pin becomes active (low) to signal that
an SMBAlert is active.
3.
4.
5.
6.
The host processor issues an SMBus alert response address
command to determine which device has an active alert.
If there are no other active alerts from devices with lower
I 2 C addresses, this device makes the GPO2/ALERT2 pin
inactive (high) during the no acknowledge bit period after
it sends its address to the host processor.
If the GPO2/ALERT2 pin stays low, the host processor must
continue to issue SMBus alert response address commands
to devices to find out the addresses of all devices whose
status it must check.
The ADM1276 continues to operate with the GPO2/ALERT2
pin inactive and the contents of the status bytes unchanged
until the host reads the status bytes and clears them, or until
a new fault occurs. That is, if a status bit for a fault/warning
that is enabled on the GPO2/ALERT2 pin and that was not
already active (equal to 1) changes from 0 to 1, a new alert
is generated, causing the GPO2/ALERT2 pin to become
active again.
Rev. C | Page 34 of 48
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