参数资料
型号: EVAL-ADM2914EBZ
厂商: Analog Devices Inc
文件页数: 11/16页
文件大小: 0K
描述: BOARD EVAL FOR ADM2914
标准包装: 1
主要目的: 电源管理,电源监控器/跟踪器/序列发生器
嵌入式:
已用 IC / 零件: ADM2914
主要属性: 电压检测器和监控器
次要属性: 开漏极输出
已供物品:
Data Sheet
Next, consider a ?12 V input, which is specified with a ±20%
input. The threshold accuracy required by the supply is chosen
to be within ±5% of the ?12 V rail. Therefore, the overvoltage
threshold is set to ?13.5 V, and the undervoltage threshold is
?10.5 V. The negative voltage scheme configuration requires
that the 1 V reference voltage be accounted for in Equation 1 to
Equation 3. The 1 V reference voltage is subtracted from V M ,
V UV , and V OV , and the absolute value of the result is taken.
ADM2914
Refer to Figure 15 in the Typical Performance Characteristics
section, which illustrates the delay time as a function of the
timer capacitor value. A minimum capacitor value of 10 pF is
required. The chosen timer capacitor must have a leakage current
that is less than the 1.3 μA TIMER pin charging current. To
bypass the timeout period, connect the TIMER pin to V CC .
VHx MONITOR TIMING
( ? 13 . 5 ? 1 ) ( 5 × 10 ? 6 )
Equation 1 becomes
( 0 . 5 ) ( ? 12 ? 1 )
R Z =
≈ 89 . 8 kΩ
VHx
V UOT
t UOD
t UOTO
( ? 10 . 5 ? 1 ) ( 5 × 10 ? 6 )
Insert the value of R Z into Equation 2.
( 0 . 5 ) ( ? 12 ? 1 )
R Y = ? 89 . 8 kΩ ≈ 23 . 4 kΩ
To calculate R X , insert the value of R Z and R Y into Equation 3.
UV
1V
VHx MONITOR TIMING (TIMER PIN TIED TO V CC )
( ? 12 ? 1 ) ? ( 89 . 8 kΩ ) ? ( 23 . 4 kΩ ) ≈ 2 . 49 MΩ
R X =
5 × 10
VHx
V UOT
POWER-UP AND POWER-DOWN
On power-up, when V CC reaches 1 V, the active low UV output
is asserted, and the OV output pulls up to V CC . When the vol-
tage on the V CC pin reaches 1 V, the ADM2914 is guaranteed to
UV
t UOD
1V
t UOD
assert UV low and OV high. When V CC exceeds 1.9 V (minimum),
the VHx and VLx inputs take control. When V CC and each of
the VHx inputs are valid, an internal timer begins. Subsequent
to an adjustable time delay, UV weakly pulls high.
UV/OV TIMING CHARACTERISTICS
WHEN AN INPUT IS CONFIGURED TO MONITOR A NEGATIVE VOLTAGE,
VHx WILL TRIGGER AN OVERVOLTAGE CONDITION.
Figure 21. VHx Positive Voltage Monitoring Timing Diagram
VLx MONITOR TIMING
UV is an active low output. It is asserted when any of the four
VLx
V UOT
monitored voltages is below its associated threshold. When the
voltage on the V CC pin is above 2 V, an internal timer holds
UV low for an adjustable period, t UOTO , after the voltage on all
the monitoring rails rises above their thresholds. This allows
time for all monitored power supplies to stabilize after power-
up. Similarly, any monitored voltage that falls below its threshold
OV
t UOD
1V
t UOTO
initiates a timer reset, and the timer starts again when all the
monitoring rails rise above their thresholds.
VLx MONITOR TIMING (TIMER PIN TIED TO V CC )
The UV and OV outputs are held asserted after all faults have
VLx
V UOT
cleared for an adjustable timeout period, determined by the
value of the external capacitor attached to the TIMER pin.
TIMER CAPACITOR SELECTION
The UV and OV timeout period on the ADM2914 is programma-
ble via the external timer capacitor, C TIMER , placed between the
OV
t UOD
1V
t UOD
TIMER pin and ground. The timeout period, t UOTO , is calculated
using the following equation:
C TIMER = ( t UOTO )( 115 )( 10 ? 9 ) F/sec
WHEN AN INPUT IS CONFIGURED TO MONITOR A NEGATIVE VOLTAGE,
VLx WILL TRIGGER AN UNDERVOLTAGE CONDITION.
Figure 22. VLx Positive Voltage Monitoring Timing Diagram
Rev. C | Page 11 of 16
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