参数资料
型号: EVAL-ADUM3223AEBZ
厂商: Analog Devices Inc
文件页数: 3/8页
文件大小: 0K
描述: BOARD EVAL FOR ADUM3223
标准包装: 1
系列: iCoupler®
主要目的: 接口,数字式隔离器
嵌入式:
已用 IC / 零件: ADuM3223
主要属性: 2 通道
次要属性: 3 V ~ 5.5 V 电源
已供物品:

Evaluation Board User Guide
SETTING UP THE EVALUATION BOARD
PAD LAYOUT FOR THE DUT
Figure 5 shows the top layer artwork for the dual gate driver circuit.
UG-368
INPUT/OUTPUT CONNECTIONS
Connect Logic Input A (V IA ) to TP1 or to Pin 1 of J1; connect
?
?
?
?
U1 is the footprint for the ADuM3223 or ADuM4223 .
C1, C2, and C4 are 0.1 μF bypass capacitors; C3 and C5
are 10 μF bypass capacitors.
Q1 and Q2 can be populated with TO-263 or TO-252
MOSFETs or IGBTs with the pinout shown in Figure 2.
C6 and C7 are 2.2 nF loads for the gate driver outputs.
Remove C6 and C7 if MOSFETs or IGBTs are added to
Q1 and Q2.
Logic Input B (V IB ) to TP2 or to Pin 2 of J1. Both inputs have
50 Ω terminations. Resistor R5 enables the outputs of the
ADuM3223 or ADuM4223 by pulling the DISABLE pin low.
The disable function can also be externally controlled from
J1 or set by J2 (not installed).
The half-bridge output is the Q1 emitter/source and Q2
collector/drain node. A wire pad labeled VOUT/GNDA is
the output of this circuit.
R6 and R7 are for gate resistors to control the edges of the out-
puts. By default, 0 Ω resistors are installed, but these resistors
may need to be replaced with low value 0603 resistors if the
outputs have loads lighter than 2 nF.
BOOTSTRAPPING V DDB TO V DDA
To bootstrap V DDB to V DDA , a through-hole diode can be connected
from V DDB to V DDA , as shown in Figure 3. In this way, both outputs
of the ADuM3223 / ADuM4223 can be powered by the V DDB supply
when a half bridge is configured with Q1 and Q2.
When the switch node (GNDA) is low, C2 and C3 are charged
through the forward biased bootstrapping diode. When the
switch node rises to the bridge voltage, the diode becomes
reverse biased, and V DDA = GNDA + V DDB ? GNDB because
of the charge on C2 and C3. For bootstrapping to work, Q1
and Q2 must be populated instead of the load capacitors, C6
and C7. The switching frequency must be sufficiently high to
supply C2 and C3 with the charge required to drive the Q1 gate.
Figure 2. IGBT/MOSFET Footprint
POWER CONNECTIONS
To connect the evaluation board to the power supply, follow
these steps:
1.
Connect the 5 V or 3.3 V input supply to J3 and its return
to J4.
Figure 3. Bootstrapping V DDB to V DDA
2.
3.
Connect the ADuM3223 / ADuM4223 V DDB supply voltage
(4.5 V to 18 V) to J7 and its return to J8.
Connect the V DDA supply voltage (4.5 V to 18 V) to J5 and
its return to J6.
GNDA and GNDB are functionally isolated. The emitter/source
of Q1 is tied to GNDA, and the emitter/source of Q2 is tied to
GNDB. GNDB also has a wire pad directly below the emitter/
source pad of Q2. Connect the bridge supply to the +HV wire
pad, which is connected to the collector/drain of Q1.
Rev. 0 | Page 3 of 8
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