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| 型号： | EVAL-ADV7842EB2Z |
| 厂商： | Analog Devices Inc |
| 文件页数： | 28/28页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADV7842EB2Z |
| 标准包装： | 1 |
| 系列： | * |
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ADV7842
Rev. B | Page 9 of 28
TIMING CHARACTERISTICS
Data and I2C Timing Characteristic
Table 5.
Parameter1
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
CLOCK AND CRYSTAL
Crystal Frequency, XTAL
28.63636
MHz
Crystal Frequency Stability
±50
ppm
Horizontal Sync Input Frequency
10
110
kHz
LLC Frequency Range
12.825
170
MHz
I2C PORTS
SCL Frequency
400
kHz
SCL Minimum Pulse Width High
t1
600
ns
SCL Minimum Pulse Width Low
t2
1.3
s
Start Condition Hold Time
t3
600
ns
Start Condition Setup Time
t4
600
ns
SDA Setup Time
t5
100
ns
SCL and SDA Rise Time
t6
1000
ns
SCL and SDA Fall Time
t7
300
ns
Stop Condition Setup Time
t8
0.6
s
TTX I2C PORTS
SCL Frequency
3.4
MHz
SCL Minimum Pulse Width High
t1
60
ns
SCL Minimum Pulse Width Low
t2
160
ns
Start Condition Hold Time
t3
160
ns
Start Condition Setup Time
t4
160
ns
SDA Setup Time
t5
10
ns
SCL and SDA Rise Time
t6
10
80
ns
SCL and SDA Fall Time
t7
10
80
ns
Stop Condition Setup Time
t8
160
ns
RESET FEATURE
Reset Pulse Width
5
ms
CLOCK OUTPUTS
LLC Mark-Space Ratio
t9:t10
45:55
55:45
% duty cycle
DATA AND CONTROL OUTPUTS2
Data Output Transition Time SDR (SDP)
t11
End of valid data to negative clock edge
2.9
4.6
ns
Data Output Transition Time SDR (SDP)
t12
Negative clock edge to start of valid data
0.2
0.6
ns
Data Output Transition Time SDR (CP)
t13
End of valid data to negative clock edge
1.5
2.2
ns
Data Output Transition Time SDR (CP)
t14
Negative clock edge to start of valid data
0.1
0.3
ns
I2S PORT, MASTER MODE
SCLK Mark-Space Ratio
t15:t16
45:55
55:45
% duty cycle
LRCLK Data Transition Time
t17
End of valid data to negative SCLK edge
10
ns
LRCLK Data Transition Time
t18
Negative SCLK edge to start of valid data
10
ns
I2Sx Data Transition Time
t19
End of valid data to negative SCLK edge
5
ns
I2Sx Data Transition Time
t20
Negative SCLK edge to start of valid data
5
ns
1
Guaranteed by characterization.
2
With the DLL block on output clock bypassed.
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