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| 型号： | EVAL-CN0194-SDPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 9/28页 |
| 文件大小： | 0K |
| 描述： | BOARD CFTL AD7685 |
| 设计资源： | CN-0194 CFTL Eval/Design Support |
| 标准包装： | 1 |
| 系列： | Circuits from the Lab™ |
| 主要目的： | 参考设计，隔离式数据采集系统 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD7685，AD8615，ADuM1402 |
| 已供物品： | 板 |
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AD7685
Rev. C | Page 17 of 28
The AD7685 powers down automatically at the end of each
conversion phase and, therefore, the power scales linearly with
the sampling rate, as shown in Figure 32. This makes the part
ideal for low sampling rate (even a few Hz) and low battery-
powered applications.
02
96
8-
0
30
SAMPLING RATE (SPS)
1000000
10
100
1000
10000
100000
OP
E
R
A
T
ING
CU
RRE
N
T
S
(
A)
1000
10
0.1
0.001
10000
100
1
0.01
VDD = 5V
VIO
VDD = 2.5V
Figure 32. Operating Currents vs. Sampling Rate
SUPPLYING THE ADC FROM THE REFERENCE
For simplified applications, the AD7685, with its low operating
current, can be supplied directly using the reference circuit, as
shown in Figure 33. The reference line can be driven by either:
The system power supply directly.
A reference voltage with enough current output capability,
such as the ADR43x.
A reference buffer, such as the AD8031, that can also filter
the system power supply, as shown in Figure 33.
AD8031
AD7685
VIO
REF
VDD
10F
1F
10
10k
5V
1F
1
02
96
8-
03
1
1OPTIONAL REFERENCE BUFFER AND FILTER.
Figure 33. Example of Application Circuit
DIGITAL INTERFACE
Though the AD7685 has a reduced number of pins, it offers
substantial flexibility in its serial interface modes.
The AD7685, when in CS mode, is compatible with SPI, QSPI,
digital hosts, and DSPs, for example, Blackfin ADSP-BF53x or
ADSP-219x. This interface can use either 3-wire or 4-wire. A
3-wire interface using the CNV, SCK, and SDO signals minimizes
wiring connections, useful, for instance, in isolated applications.
A 4-wire interface using the SDI, CNV, SCK, and SDO signals
allows CNV, which initiates the conversions, to be independent
of the readback timing (SDI). This is useful in low jitter
sampling or simultaneous sampling applications.
The AD7685, when in chain mode, provides a daisy-chain
feature using the SDI input for cascading multiple ADCs on a
single data line similar to a shift register.
The mode in which the part operates depends on the SDI level
when the CNV rising edge occurs. The CS mode is selected if
SDI is high and the chain mode is selected if SDI is low. The
SDI hold time is such that when SDI and CNV are connected
together, the chain mode is always selected.
In either the CS mode or the chain mode, the AD7685 offers the
flexibility to optionally force a start bit in front of the data bits.
This start bit can be used as a BUSY signal indicator to
interrupt the digital host and trigger the data reading.
Otherwise, without a BUSY indicator, the user must time out
the maximum conversion time prior to readback.
The BUSY indicator feature is enabled as follows:
In the CS mode, if CNV or SDI is low when the ADC
conversion ends (see
and
).
In the chain mode, if SCK is high during the CNV rising edge
(see Figure 45).
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