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参数资料
| 型号： | EVAL-SSM2518Z |
| 厂商： | Analog Devices Inc |
| 文件页数： | 10/48页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR SSM2518 |
| 标准包装： | 1 |
| 系列： | * |
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SSM2518
Data Sheet
Rev. A | Page 18 of 48
Register 0x0A. The entire DRC function can be enabled or
disabled using DRC_EN (Bits[1:0] of Register 0x0A).
Linear Region
For input amplitudes between the DRC_ET and DRC_CT
thresholds, the DRC attenuation is set to zero, that is, the input is
passed straight through to the output. This is the region in the
center of the compression curve (see Figure 25) with a 1:1 slope,
where the input and output amplitude are the same.
Compressor
Above the input level set by DRC_CT (Bits[3:0] of Reg-
ister 0x0C), the output amplitude does not rise as quickly as
the input. This provides a smooth transition to the limiter
region, where the output stops increasing altogether at the input
level set by DRC_LT (Bits[7:4] of Register 0x0C). At this point,
the output level is DRC_SMAX (Bits[7:4] of Register 0x0E).
Limiter
When the input level is above the input level set by DRC_LT,
the output level does not exceed the level given by DRC_SMAX
(Bits[7:4] of Register 0x0E). Instead, the overall gain is reduced
to maintain that level without clipping.
Expander
When the expander is enabled and the input level falls below
the level set by DRC_ET (Bits[7:4] of Register 0x0D), the output
level begins to decrease more rapidly than the input. This
provides a smooth transition to the noise gate, where
sufficiently small signals are blocked completely.
When the input signal falls to the level set by DRC_NT
(Bits[3:0] of Register 0x0D), the output level is set by
DRC_SMIN (Bits[3:0] of Register 0x0E).
Noise Gate
When the noise gate is enabled and the input signal level falls
below the threshold set by DRC_NT for a period of time, the
output is set to zero. Set this at a level lower than all signals of
interest to block the output in periods of silence.
The period of time for which the input level must remain
below the noise gate threshold prior to the output setting to
zero is determined by HDT_NG, Bits[3:0] of Register 0x10.
Attack and Decay Rates
To prevent audible distortion effects as the gain changes, the
time constants for the attack (gain reduction) and decay (gain
increase) are adjustable. The attack time is set by DRC_ATT
(Bits[7:4] of Register 0x0F), and the decay time is set by
DRC_DEC (Bits[3:0] of Register 0x0F).
Between attack and decay, a hold time is used to prevent rapid
switching between increased gain and decreased gain. The hold
time is set by HDT_NOR (Bits[7:4] of Register 0x10).
Post-DRC Gain
Because the DRC feature may have an overall effect on the
system gain, a separate digital gain option is provided to allow
the user to compensate for this effect. This digital gain option is
independent of the volume control feature, allowing an overall
gain adjustment that remains separate from the volume settings.
This level is set by DRC_POST_G (Bits[5:2] of Register 0x11).
Depending on the application, the entire DRC block can be placed
before or after the volume controls (L_VOL and R_VOL). This
option is set by PRE_VOL (Bit 6 of Register 0x0A).
MUTE OPTIONS
Several mute options are available. Each channel can be muted
independently using the left channel mute (L_MUTE, Bit 1 of
Register 0x07) or the right channel mute (R_MUTE, Bit 2 of
Register 0x07). Alternatively, both channels can be muted
simultaneously using the master mute option (M_MUTE, Bit 0
of Register 0x07).
The master mute is enabled at system startup; therefore, it must
be disabled before any audio is produced.
The SSM2518 also contains an automatic mute feature. This
feature is enabled by setting AMUTE (Bit 7 of Register 0x07).
When active, this feature monitors the incoming digital audio
signal. When the data stream is zero for 2048 consecutive
frames (1024 stereo samples), the output is muted. When a
single nonzero input is received on the I2S interface, the
SSM2518 is unmuted and resumes normal operation.
VOLUME CONTROL
The SSM2518 has a digital volume control that allows indepen-
dent control of the left and right channels via Registers 0x05
and 0x06, respectively. 255 levels are available, providing a
range from +24 dB to 71.25 dB in 0.375 dB increments. This is
a soft volume control, meaning that the gain is adjusted contin-
uously from one value to another. This continuously adjusted
gain prevents the audible pop that occurs with an instantaneous
gain adjustment.
When VOL_LINK (Bit 3 in Register 0x07) is set, both channels
are linked to the left channel volume setting.
DE-EMPHASIS FILTER
A digital de-emphasis filter is provided to compensate for the
standard compact disc style preemphasis, which occurs in some
audio systems. This filter is designed for use with a 44.1 kHz
sample rate only. To enable the de-emphasis filter, set
DEEMP_EN (Bit 4 of Register 0x07).
ANALOG GAIN
The analog gain of the SSM2518 amplifier is set by ANA_GAIN
(Bit 5 of Register 0x07). Each gain setting is designed to match
the scaling needed for a specified PVDD voltage so that the
digital full-scale values correspond to the clipping points of the
amplifier at that voltage.
If PVDD is larger than the voltage specified in this register, the
digital scale does not fill the output voltage range and maximum
output power is reduced. Similarly, if PVDD is smaller than
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