参数资料
| 型号： | EX64-FTQG100 |
| 厂商： | Microsemi SoC |
| 文件页数： | 7/48页 |
| 文件大小： | 0K |
| 描述： | IC FPGA ANTIFUSE 3K 100-TQFP |
| 标准包装： | 90 |
| 系列： | EX |
| 逻辑元件/单元数： | 128 |
| 输入/输出数： | 56 |
| 门数： | 3000 |
| 电源电压： | 2.3 V ~ 2.7 V |
| 安装类型： | 表面贴装 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 100-LQFP |
| 供应商设备封装： | 100-TQFP（14x14） |
第1页第2页第3页第4页第5页第6页当前第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页
eX Family FPGAs
Revision 10
1-11
Table 1-5 describes the different configuration requirements of BST pins and their functionality in different
modes.
TRST Pin
The TRST pin functions as a dedicated Boundary-Scan Reset pin when the Reserve JTAG Test Reset
option is selected, as shown in Figure 1-12. An internal pull-up resistor is permanently enabled on the
TRST pin in this mode. It is recommended to connect this pin to GND in normal operation to keep the
JTAG state controller in the Test-Logic-Reset state. When JTAG is being used, it can be left floating or be
driven HIGH.
When the Reserve JTAG Test Reset option is not selected, this pin will function as a regular I/O. If
unused as an I/O in the design, it will be configured as a tristated output.
JTAG Instructions
Table 1-6 lists the supported instructions with the corresponding IR codes for eX devices.
Table 1-7 lists the codes returned after executing the IDCODE instruction for eX devices. Note that bit 0
is always “1.” Bits 11-1 are always “02F”, which is Microsemi SoC Products Group's manufacturer code.
Table 1-5 Boundary-Scan Pin Configurations and Functions
Mode
Designer "Reserve JTAG" Selection
TAP Controller State
Dedicated (JTAG)
Checked
Any
Flexible (User I/O)
Unchecked
Test-Logic-Reset
Flexible (JTAG)
Unchecked
Any EXCEPT Test-Logic-Reset
Table 1-6 JTAG Instruction Code
Instructions (IR4: IR0)
Binary Code
EXTEST
00000
SAMPLE / PRELOAD
00001
INTEST
00010
USERCODE
00011
IDCODE
00100
HIGHZ
01110
CLAMP
01111
Diagnostic
10000
BYPASS
11111
Reserved
All others
Table 1-7 IDCODE for eX Devices
Device
Revision
Bits 31-28
Bits 27-12
eX64
0
8
40B2, 42B2
eX128
0
9
40B0, 42B0
eX256
0
9
40B5, 42B5
eX64
1
A
40B2, 42B2
eX128
1
B
40B0, 42B0
eX256
1
B
40B5, 42B5
相关PDF资料 |
PDF描述 |
|---|---|
| EX64-FTQ100 | IC FPGA ANTIFUSE 3K 100-TQFP |
| BR24L02FJ-WE2 | IC EEPROM 2KBIT 400KHZ 8SOP |
| A3PN030-Z1VQG100I | IC FPGA NANO 30K GATES 100-VQFP |
| A3P030-1VQG100I | IC FPGA 1KB FLASH 30K 100-VQFP |
| A3PN030-Z1VQ100I | IC FPGA NANO 30K GATES 100-VQFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EX64-FTQG100A | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:eX Automotive Family FPGAs |
| EX64-FTQG100I | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:eX Family FPGAs |
| EX64-FTQG100PP | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:eX Family FPGAs |
| EX64-FTQG64 | 功能描述:IC FPGA ANTIFUSE 3K 64-TQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:EX 标准包装:152 系列:IGLOO PLUS LAB/CLB数:- 逻辑元件/单元数:792 RAM 位总计:- 输入/输出数:120 门数:30000 电源电压:1.14 V ~ 1.575 V 安装类型:表面贴装 工作温度:-40°C ~ 85°C 封装/外壳:289-TFBGA，CSBGA 供应商设备封装:289-CSP（14x14） |
| EX64-PCS100 | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:eX Automotive Family FPGAs |
发布紧急采购，3分钟左右您将得到回复。