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参数资料
| 型号： | EZ4021 |
| 英文描述： | EZ4021 MiniRISC microprocessor core |
| 中文描述： | EZ4021 MiniRISC微处理器核心 |
| 文件页数： | 2/2页 |
| 文件大小： | 49K |
| 代理商： | EZ4021 |
LSI Logic logo design, CoreWare and MiniRisc are registered
trademarks and EasyMacro is a trademark of LSI Logic
Corporation. All other brand and product names may be
trademarks of their respective companies.
LSI Logic Corporation reserves the right to make changes to
any products and services herein at any time without notice.
LSI Logic does not assume any responsibility or liability aris-
ing out of the application or use of any product or service
described herein, except as expressly agreed to in writing by
LSI Logic; nor does the purchase, lease, or use of a product or
service from LSI Logic convey a license under any patent
rights, copyrights, trademark rights, or any other of the intel-
lectual property rights of LSI Logic or of third parties.
Copyright 2000 by LSI Logic Corporation.
All rights reserved.
For more information please call:
Europe +32.11.300.351
www.lsilogic.com
LSI Logic Corporation
North American Headquarters
Milpitas, CA
Tel: 800.574.4286
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European Headquarters
United Kingdom
Tel: 44.1344.426544
Fax: 44.1344.481039
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Tokyo, Japan
Tel: 81.3.5463.7821
Fax: 81.3.5463.7820
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EZ4021 Description
The EZ4021 EasyMACRO is an optimized implementation of a synthesizeable
core that operates up to 250MHz, under worst case conditions. The EZ4021 core
integrates a complete CPU and CPU subsystem. The CPU implements the MIPS III
instruction set architecture (ISA). The CPU subsystem is comprised of a memory
management unit, multiply-divide unit, system-coprocessor, bus interface unit,
separate 16K instruction and 16K data caches, non- intrusive EJTAG debug module.
Both CPU and CPU subsystem are integrated into the compact 12-sq. mm
EZ4021 core.
Performance features of the EasyMACRO include MAC instruction extensions,
hardware instruction prefetch and streaming and a high-performance bus inter-
face. The memory management unit, designed for Windows CE compliance,
includes dual 32 entry TLBs, supporting variable page sizes ranging from 4K-16M.
The Bus Interface Unit controls the on-chip system bus. Operating up to 125MHz,
the split transaction bus (32-bit address, 64 bit data), provides a glueless interface
to optional external building blocks. These CoreWare library blocks, external
to the EasyMACRO, include SDRAM controller, off-chip bus controller,
and UART.
Support Products
The EZ4021 MiniRISC MIPS core supports MIPS-III instructions and leverages
the widely available industry standard, low cost, third party tools developed in
support of the MIPS architecture. In addition, the EZ4021 leverages both mature
debug capability and third party tool chains that are supported by LSI Logic.
A complete evaluation and development kit is available for the EZ4021
EasyMACRO MIPS processor. The kit includes an EZ4021 development board,
an EJTAG probe, third party tool chain, software examples and documentation.
CoreWare Design Program
The EZ4021 MiniRISC is a member of the LSI Logic CoreWare IP library.
This CoreWare methodology provides an extensive selection of proven IP
enabling rapid system-on-a-chip design integration. The EZ4021 deliverables
include a Verilog compatible RTL model, a system verification environment
(SVE), complete netlist, timing and example script files with layout to
accelerate ASIC SoC development.
Order No. R20023
600.1K.JH.TP – Printed in USA
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