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参数资料
| 型号： | FAB2200UCX |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 2/18页 |
| 文件大小： | 0K |
| 描述： | IC SUBSYSTEM HDPH AMP G 25-WLCSP |
| 标准包装： | 1 |
| 类型： | D 类；G 类 |
| 输出类型： | 1-通道（单声道），带立体声耳机 |
| 在某负载时最大输出功率 x 通道数量： | 1.2W x 1 @ 8 欧姆; 41mW x 2 @ 32 欧姆 |
| 电源电压： | 2.8 V ~ 5.25 V |
| 特点： | 消除爆音，差分输入，I²C，静音，短路和热保护，关机，音量控制 |
| 安装类型： | 表面贴装 |
| 供应商设备封装： | 25-WLCSP |
| 封装/外壳： | 25-UFBGA，WLCSP |
| 包装： | 标准包装 |
| 其它名称： | FAB2200UCXFSDKR |
10
COMMERCIALTEMPERATURERANGE
IDT72V70180 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 128 x 128
TABLE 8 — FRAME INPUT OFFSET REGISTER (FOR) BITS
NOTE:
1. n denotes an input stream number from 0 to 3.
Name(1)
Description
OFn2, OFn1, OFn0
These three bits define how long the serial interface receiver takes to recognize and store bit 0 from the RX input pin: i.e., to
(Offset Bits 2, 1 & 0)
start a new frame. The input frame offset can be selected to +4.5 clock periods from the point where the external frame pulse
input signal is applied to the
F0i input of the device. See Figure 5.
DLEn
(Data Latch Edge)
ST-BUS mode:
DLEn = 0, if clock rising edge is at the point of the bit cell.
DLEn = 1, if when clock falling edge is at the of the bit cell.
GCI mode:
DLEn = 0, if clock falling edge is at the point of the bit cell.
DLEn = 1, if when clock rising edge is at the of the bit cell.
Read/Write Address:
03H.
Reset Value:
0000H.
15
14
13
12
11
10
9876543210
OF32
OF31
OF30
DLE3
OF22
OF21
OF20
DLE2
OF12
OF11
OF10
DLE1
OF02
OF01
OF00
DLE0
FOR Register
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