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| 型号： | FAN3122TMPX |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 15/21页 |
| 文件大小： | 0K |
| 描述： | IC GATE DVR SGL 9A LOSIDE 8-MLP |
| 特色产品： | FAN3111/FAN3121/FAN3122 Single 1A & 9A High Speed, Low-Side Gate Drivers |
| 标准包装： | 1 |
| 配置： | 低端 |
| 输入类型： | 非反相 |
| 延迟时间： | 23ns |
| 电流 - 峰： | 11.4A |
| 配置数： | 1 |
| 输出数： | 1 |
| 电源电压： | 4.5 V ~ 18 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-MLP |
| 供应商设备封装： | 8-MLP（3x3） |
| 包装： | 标准包装 |
| 其它名称： | FAN3122TMPXDKR FAN3122TMPXDKR-ND FAN3122TMPXFSDKR |
Figure 47 shows the pulsed gate drive current path
when the gate driver is supplying gate charge to turn the
MOSFET on. The current is supplied from the local
bypass capacitor C BYP and flows through the driver to
the MOSFET gate and to ground. To reach the high
peak currents possible with the FAN312x family, the
resistance and inductance in the path should be
minimized. The localized C BYP acts to contain the high
peak current pulses within this driver-MOSFET circuit,
preventing them from disturbing the sensitive analog
V DD
IN-
Turn-on threshold
circuitry in the PWM controller.
V DD
C BYP
FAN3121/2
V DS
IN+
(V DD )
OUT
PWM
Figure 50. Inverting Startup Waveforms
Figure 47. Current Path for MOSFET Turn-On
Figure 48 shows the path the current takes when the gate
driver turns the MOSFET off. Ideally, the driver shunts the
current directly to the source of the MOSFET in a small
circuit loop. For fast turn-off times, the resistance and
inductance in this path should be minimized.
V DD V DS
At power up, the FAN3122 non-inverting driver, shown
in Figure 51, holds the output LOW until the V DD voltage
reaches the UVLO turn-on threshold, as indicated in
Figure 52. The OUT pulses magnitude follow V DD
magnitude until steady-state V DD is reached.
V DD
C BYP
FAN3121/2
IN
OUT
PWM
Figure 51. Non-Inverting Driver
Figure 48. Current Path for MOSFET Turn-Off
Operational Waveforms
At power up, the FAN3121 inverting driver shown in
Figure 49 holds the output LOW until the V DD voltage
reaches the UVLO turn-on threshold, as indicated in
Figure 50. This facilitates proper startup control of low-
side N-channel MOSFETs.
V DD
IN
OUT
V DD
IN-
IN+
Turn-on threshold
OUT
Figure 49. Inverting Configuration
The OUT pulses’ magnitude follows V DD magnitude with
the output polarity inverted from the input until steady-
state V DD is reached.
? 2008 Fairchild Semiconductor Corporation
FAN3121 / FAN3122 ? Rev. 1.0.3
15
Figure 52. Non-Inverting Startup Waveforms
www.fairchildsemi.com
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