参数资料
型号: FAN3224TMPX
厂商: Fairchild Semiconductor
文件页数: 20/27页
文件大小: 0K
描述: IC GATE DVR DUAL 4A 8-MLP
标准包装: 1
配置: 低端
输入类型: 非反相
延迟时间: 17ns
电流 - 峰: 5A
配置数: 2
输出数: 2
电源电压: 4.5 V ~ 18 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 8-MLP
供应商设备封装: 8-MLP(3x3)
包装: 标准包装
其它名称: FAN3224TMPXDKR
V DD Bypass Capacitor Guidelines
To enable this IC to turn a device ON quickly, a local
high-frequency bypass capacitor, C BYP , with low ESR
and ESL should be connected between the VDD and
?
For best results, make connections to all pins as
short and direct as possible.
The FAN322x is compatible with many other
industry-standard drivers. In single input parts with
GND pins with minimal trace length. This capacitor is
in addition to the bulk electrolytic capacitance of 10 μF
to 47 μF commonly found on the driver and controller
bias circuits.
A typical criterion for choosing the value of C BYP is to
keep the ripple voltage on the V DD supply to ≤ 5%. This
is often achieved with a value ≥ 20 times the equivalent
load capacitance C EQV , defined here as Q GATE /V DD .
Ceramic capacitors of 0.1 μF to 1 μF or larger are
common choices, as are dielectrics, such as X5R and
X7R with good temperature characteristics and high
pulse current capability.
If circuit noise affects normal operation, the value of
C BYP may be increased to 50-100 times the C EQV , or
C BYP may be split into two capacitors. One should be a
larger value, based on equivalent load capacitance, and
the other a smaller value, such as 1-10 nF mounted
closest to the VDD and GND pins to carry the higher
frequency components of the current pulses. The
bypass capacitor must provide the pulsed current from
both of the driver channels and, if the drivers are
switching simultaneously, the combined peak current
sourced from the C BYP would be twice as large as when
a single channel is switching.
Layout and Connection Guidelines
The FAN3223-25 family of gate drivers incorporates
fast-reacting input circuits, short propagation delays,
and powerful output stages capable of delivering current
peaks over 4 A to facilitate voltage transition times from
under 10 ns to over 150 ns. The following layout and
connection guidelines are strongly recommended:
enable pins, there is an internal 100 k ? resistor tied
to VDD to enable the driver by default; this should
be considered in the PCB layout.
? The turn-on and turn-off current paths should be
minimized, as discussed in the following section.
Figure 48 shows the pulsed gate drive current path
when the gate driver is supplying gate charge to turn the
MOSFET ON. The current is supplied from the local
bypass capacitor, C BYP , and flows through the driver to
the MOSFET gate and to ground. To reach the high
peak currents possible, the resistance and inductance in
the path should be minimized. The localized C BYP acts
to contain the high peak current pulses within this driver-
MOSFET circuit, preventing them from disturbing the
sensitive analog circuitry in the PWM controller.
Figure 48. Current Path for MOSFET Turn-On
?
?
?
?
Keep high-current output and power ground paths
separate logic and enable input signals and signal
ground paths. This is especially critical when
dealing with TTL-level logic thresholds at driver
inputs and enable pins.
Keep the driver as close to the load as possible to
minimize the length of high-current traces. This
reduces the series inductance to improve high-
speed switching, while reducing the loop area that
can radiate EMI to the driver inputs and
surrounding circuitry.
If the inputs to a channel are not externally
connected, the internal 100 k ? resistors indicated
on block diagrams command a low output. In noisy
environments, it may be necessary to tie inputs of
an unused channel to VDD or GND using short
traces to prevent noise from causing spurious
output switching.
Many high-speed power circuits can be susceptible
to noise injected from their own output or other
external sources, possibly causing output re-
triggering. These effects can be obvious if the
circuit is tested in breadboard or non-optimal circuit
layouts with long input, enable, or output leads.
Figure 49 shows the current path when the gate driver
turns the MOSFET OFF. Ideally, the driver shunts the
current directly to the source of the MOSFET in a small
circuit loop. For fast turn-off times, the resistance and
inductance in this path should be minimized.
Figure 49. Current Path for MOSFET Turn-Off
? 2007 Fairchild Semiconductor Corporation
FAN3223 / FAN3224 / FAN3225 ? Rev. 1.1.4
20
www.fairchildsemi.com
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