参数资料
型号: FAN5236QSC
厂商: Fairchild Semiconductor
文件页数: 4/19页
文件大小: 0K
描述: IC CTRLR DDR/PWM DUAL HE 28QSOP
产品变化通告: Lead Dimensions Change 30/Oct/2007
标准包装: 2,350
应用: 控制器,移动式 DDR
输入电压: 5 V ~ 24 V
输出数: 2
输出电压: 0.9 V ~ 5 V
工作温度: -10°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 28-QSOP
包装: 管件
其它名称: FAN5236QSC_NL
FAN5236QSC_NL-ND
Pin Descriptions (Continued)
Pin #
13
14
15
16
Name
DDR
VIN
PG1
PG2 /
REF2OUT
Description
DDR Mode Control . HIGH = DDR Mode. LOW = two separate regulators operating 180° out
of phase.
Input Voltage . Normally connected to battery, providing voltage feedforward to set the
amplitude of the internal oscillator ramp. When using the IC for two-step conversion from 5V
input, connect through 100K Ω resistor to ground, which sets the appropriate ramp gain and
synchronizes the channels 90° out of phase.
Power Good Flag . An open-drain output that pulls LOW when V SEN is outside a ±10%
range of the 0.9V reference.
Power Good 2 . When not in DDR Mode, open-drain output that pulls LOW when the V OUT is
out of regulation or in a fault condition.
Reference Out 2 . When in DDR Mode, provides a buffered output of REF2. Typically used
as the V DDQ/2 reference.
Current Limit 2 . When not in DDR Mode, a resistor from this pin to GND sets the current
18
ILIM2 / REF2 limit.
Reference for reg #2 when in DDR Mode. Typically set to V OUT1 / 2 .
VCC . This pin powers the chip as well as the LDRV buffers. The IC starts to operate when
28
VCC
voltage on this pin exceeds 4.6V (UVLO rising) and shuts down when it drops below 4.3V
(UVLO falling).
? 2002 Fairchild Semiconductor Corporation
FAN5236 ? Rev. 1.3.2
4
www.fairchildsemi.com
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