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参数资料
| 型号： | FAN5355UC03X |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 21/26页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 1A 12WLCSP |
| 标准包装： | 1 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.75 V ~ 1.54 V |
| 输入电压： | 2.7 V ~ 5.5 V |
| 频率 - 开关： | 3MHz |
| 电流 - 输出： | 1A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 12-UFBGA，WLCSP |
| 包装： | 标准包装 |
| 供应商设备封装： | 12-WLCSP |
| 产品目录页面： | 1215 (CN2011-ZH PDF) |
| 其它名称： | FAN5355UC03XDKR |
SDA
T HD;STA
Slave Address
MS Bit
The master then generates a repeated-start condition (Figure
44) that causes all slaves on the bus to switch to HS mode.
The master then sends I 2 C packets, as described above,
using the HS-mode clock rate and timing.
SCL
Figure 42. Start Bit
The bus remains in HS mode until a stop bit (Figure 43) is
sent by the master. While in HS mode, packets are separated
by repeated-start conditions (Figure 44).
A transaction ends with a “STOP” condition, which is defined
Slave Releases
t SU;STA
t HD;STA
as SDA transitioning from 0 to 1 with SCL HIGH, as shown in
Figure 43.
SDA
ACK(0) or
NACK(1)
SLADDR
MS Bit
SDA
Slave Releases
ACK(0) or
NACK(1)
Master Drives
t HD;STO
SCL
Figure 44. Repeated-Start Timing
SCL
Read and Write Transactions
The following figures outline the sequences for data read and
and
defined as
Figure 43. Stop Bit
During a read from the FAN5355 (Figure 46), the master
issues a “Repeated Start” after sending the register address
and before resending the slave address. The “Repeated Start”
is a 1 to 0 transition on SDA while SCL is HIGH, as shown in
write. Bus control is signified by the shading of the packet,
Master Drives Bus Slave Drives Bus
All addresses and data are MSB first.
Symbol Definition
.
Figure 44.
High-Speed (HS) Mode
The protocols for High-Speed (HS), Low-Speed (LS), and
Fast-Speed (FS) modes are identical, except the bus speed
for HS mode is 3.4MHz. HS mode is entered when the bus
master sends the HS master code 00001XXX after a start
condition. The master code is sent in FS mode (less than
400KHz clock) and slaves do not ACK this transmission.
S
A
A
R
P
Table 9.
START, see Figure 42 .
ACK. The slave drives SDA to 0 to acknowledge
the preceding packet.
NACK. The slave sends a 1 to NACK the
preceding packet.
Repeated START, see Figure 44 .
STOP, see Figure 43 .
I 2 C Bit Definitions for Figure 45 - Figure 46
7 bits
0
8 bits
0
8 bits
0
S
Slave Address
0
A
Reg Addr
A
Data
A
P
Figure 45. Write Transaction
7 bits
0
8 bits
0
7 bits
0
8 bits
1
S
Slave Address
0
A
Reg Addr
A
R
Slave Address
1
A
Data
A
P
Figure 46. Read Transaction
? 2008 Fairchild Semiconductor Corporation
FAN5355 ? Rev. 1.1.0
21
www.fairchildsemi.com
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