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参数资料
| 型号： | FAN6210MY |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 8/11页 |
| 文件大小： | 0K |
| 描述： | IC CTLR RECT SYNC TRIGGER 8-SOIC |
| 标准包装： | 2,500 |
| 应用： | 电源 |
| 输入电压： | 10.5 V ~ 24.5 V |
| 电源电压： | 7 V ~ 24 V |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOICN |
| 包装： | 带卷 (TR) |
Heavy load condition
SIN
SOUT
XP
300n s
50n s
Programmable delay
700ns
100ns
50ns
700ns
300ns
Programmable delay
50n s
XN
300ns
50ns
300ns
300n s
Gate drive for Powering SR
Gate drive for Free-wheeling SR
DET
Light load condition
SIN
SOUT
300n s
Programmable delay
100ns
50ns
300ns
XP
50n s
700ns
700ns
Programmable delay
50n s
XN
300ns
50ns
300ns
300n s
Gate drive for Powering SR
Gate drive for Free-wheeling SR
DET
Figure 16. Timing Diagram
Under-Voltage Lockout (UVLO)
The power-on and -off threshold of FAN6210 are fixed
at 10V and 8V, respectively. The VDD pin can be
connected with the power source of the PWM controller.
V DD Pin Over-Voltage Protection
V DD over-voltage protection prevents damage due to
abnormal conditions. Once the V DD voltage exceeds the
V DD over-voltage protection voltage (V DD-OVP ) and lasts
for t OVP , FAN6210 stops operation .
Green-Mode Operation
To improve light-load efficiency, green-mode operation
is employed, which disables the SR turn-on trigger
signal, minimizing gate drive power consumption at
light-load condition. Green mode is enabled when the
Figure 17. Programmable Delay with Resistor
? 2009 Fairchild Semiconductor Corporation
FAN6210 Rev. 1.0.2
8
duty cycle of SIN is smaller than 10%.
www.fairchildsemi.com
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