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参数资料
| 型号： | FAN6300AMY |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 12/14页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR FLYBK ISO PWM 8SOIC |
| 标准包装： | 1 |
| PWM 型： | 电流模式 |
| 输出数： | 1 |
| 频率 - 最大： | 100kHz |
| 电源电压： | 8 V ~ 25 V |
| 降压： | 无 |
| 升压： | 无 |
| 回扫： | 是 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 是 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 包装： | 标准包装 |
| 其它名称： | FAN6300AMYDKR |
Current Sensing and PWM Current Limiting
Peak-current-mode control is utilized to regulate output
voltage and provide pulse-by-pulse current limiting. The
switch current is detected by a sense resistor into the CS
pin. The PWM duty cycle is determined by this current-
sense signal and V FB . When the voltage on CS reaches
around V LIMIT = (V FB -1.2)/3, the switch cycle is terminated
immediately. V LIMIT is internally clamped to a variable
voltage around 0.85 V for output power limit.
Leading-Edge Blanking (LEB)
Each time the power MOFFET switches on, a turn-on
spike occurs on the sense resistor. To avoid premature
termination of the switching pulse, lead-edge blanking time
is built in. During the blanking period, the current limit
comparator is disabled; it cannot switch off the gate driver.
Under-Voltage Lockout (UVLO)
The turn-on, PWM-off, and turn-off thresholds are fixed
internally at 16/10/8 V. During startup, the startup
capacitor must be charged to 16 V through the startup
resistor to enable the IC. The hold-up capacitor
continues to supply V DD until energy can be delivered
from the auxiliary winding of the main transformer. V DD
must not drop below 10 V during this startup process.
This UVLO hysteresis window ensures that hold-up
capacitor is adequate to supply V DD during startup.
Gate Output
The BiCMOS output stage is a fast totem-pole gate
driver. Cross conduction has been avoided to minimize
heat dissipation, increase efficiency, and enhance
reliability. The output driver is clamped by an internal
18 V Zener diode to protect power MOSFET transistors
against undesired over-voltage gate signals.
Over-Power Compensation
To compensate this variation for wide AC input range,
the DET pin produces an offset voltage to compensate
the threshold voltage of the peak current limit to provide
a constant-power limit. The offset is generated in
accordance with the input voltage when PWM signal is
enabled. This results in a lower current limit at high-line
inputs than low-line inputs. At fixed-load condition, the
CS limit is higher when the value of R DET is higher. R DET
also affects the H/L line constant power limit.
V DD Over-Voltage Protection
V DD over-voltage protection prevents damage due to
abnormal conditions. Once the V DD voltage is over the
V DD over-voltage protection voltage (V DD-OVP ) and lasts
for t VDDOVP , the PWM pulse is disabled until the V DD
voltage drops below the UVLO, then starts again.
Output Over-Voltage Protection
The output over-voltage protection works by the
sampling voltage, as shown in Figure 23, after switch-off
sequence. A 4 μ s (1.5 μ s for H version) blanking time
ignores the leakage inductance ringing. A voltage
comparator and a 2.5 V reference voltage develop an
output OVP protection. The ratio of the divider
determines the sampling voltage of the stop gate, as an
optical coupler and secondary shunt regulator are used.
If the DET pin OVP is triggered, the power system enters
latch-mode until AC power is removed.
Figure 23. Voltage Sampled After 4 μ s
(1.5 μ s for FAN6300H version) Blanking Time
After Switch-Off Sequence
Short-Circuit and Open-Loop Protection
The FB voltage increases every time the output of the
power supply is shorted or overloaded. If the FB voltage
remains higher than a built-in threshold for longer than t D-
OLP , PWM output is turned off. As PWM output is turned-
off, the supply voltage V DD begins decreasing.
When V DD goes below the PWM-off threshold of 10 V,
V DD decreases to 8 V, then the controller is totally shut
down. V DD is charged up to the turn-on threshold voltage
of 16 V through the startup resistor until PWM output is
restarted. This protection feature continues as long as
the overloading condition persists. This prevents the
power supply from overheating due to overloading.
Figure 22. H/L Line Constant Power Limit
Compensated by DET Pin
? 2009 Fairchild Semiconductor Corporation
FAN6300A / FAN6300H ? Rev. 1.0.2
12
www.fairchildsemi.com
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相关代理商/技术参数 |
参数描述 |
|---|---|
| FAN6300ANY | 功能描述:电流型 PWM 控制器 HI-INTEGRD QUASI-RES CURR MODE PWM RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| FAN6300DY | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| FAN6300DZ | 功能描述:电流型 PWM 控制器 Quasi-Resonant Crnt. Mode PWM Cont. RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| FAN6300H | 制造商:FAIRCHILD 制造商全称:Fairchild Semiconductor 功能描述:Highly Integrated Quasi-Resonant Current Mode PWM Controller |
| FAN6300HMY | 功能描述:开关变换器、稳压器与控制器 Hi-Int QuasiResonant Curr Mode PWM Cont RoHS:否 制造商:Texas Instruments 输出电压:1.2 V to 10 V 输出电流:300 mA 输出功率: 输入电压:3 V to 17 V 开关频率:1 MHz 工作温度范围: 安装风格:SMD/SMT 封装 / 箱体:WSON-8 封装:Reel |
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