参数资料
型号: FAN73892MX
厂商: Fairchild Semiconductor
文件页数: 13/17页
文件大小: 0K
描述: IC GATE DVR HALF BRDG 3PH 28SOIC
标准包装: 1,000
配置: 3 相桥
输入类型: 反相
延迟时间: 500ns
电流 - 峰: 350mA
配置数: 1
输出数: 3
高端电压 - 最大(自引导启动): 600V
电源电压: 10 V ~ 20 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 28-SOIC(0.295",7.50mm 宽)
供应商设备封装: 28-SOIC
包装: 带卷 (TR)
Applications Information
1. Dead Time
Dead time is automatically inserted whenever the dead
time of th e external two input signals (between HINx
and LINx signals) is shorter than internal fixed dead
times (DT1 and DT2). Otherwise, external dead times
larger than internal dead times are not modified by the
gate driver and internal dead-time waveform definition is
shown in Figure 37.
LINx
2.2 Shoot-Through Protection
The shoot-through protection circuitry prevents both
high- and low-side switches from conducting at the
same time, as shown Figure 39.
HINx
LINx
Shoot-Through
HINx
50%
50%
50%
50%
HOx
Prevent
After DT
LOx
LOx
After DT
HOx
DT1
50%
DT2
50%
Example A
HINx
Figure 37. Internal Dead-Time Definitions
2. Protection Function
2.1 Fault Out ( FO ) and Under-Voltage Lockout
The high- and low-side drivers include under-voltage
LINx
Shoot-Through
Prevent
lockout (UVLO) protection circuitry that monitors the
supply voltage for V DD and V BS independently. It can be
designed to prevent malfunction when V DD and V BS are
lower than the specified threshold voltage. The UVLO
hysteresis prevents chattering during power-supply
HOx
LOx
After DT
transitions. Moreover, the fault signal (power supply
voltage FO ) goes to LOW state to operate reliably
during power-on events when the power supply (V DD ) is
below the under-voltage lockout high threshold voltage
for the circuit (during t 1 ~ t 2 ). The UVLO circuit is not
otherwise activated; shown Figure 38.
Example B
Figure 39. Shoot-Through Protection
2.3 Enable Input
When the EN pin is in HIGH state, the gate driver
operates normally. When a condition occurs that should
shut down the gate driver, the EN pin should be LOW.
The enable circuitry has an input filter; the minimum
input duration is specified by t FLTIN (typically 250 ns).
Figure 38. Waveforms for Under-Voltage Lockout
Figure 40. Output Enable Timing Waveform
? 2011 Fairchild Semiconductor Corporation
FAN73892 ? Rev.1.0.3
13
www.fairchildsemi.com
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