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参数资料
| 型号： | FAN73933MX |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 15/17页 |
| 文件大小： | 0K |
| 描述： | IC GATE DVR HALF BRIDGE 14-SOIC |
| 标准包装： | 3,000 |
| 配置： | 半桥 |
| 输入类型： | 非反相 |
| 延迟时间： | 160ns |
| 电流 - 峰： | 2.5A |
| 配置数： | 1 |
| 输出数： | 2 |
| 高端电压 - 最大（自引导启动）： | 600V |
| 电源电压： | 10 V ~ 20 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 14-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 14-SOIC（窄型） |
| 包装： | 带卷 (TR) |
The FAN73933 has a negative V S transient performance
curve, as shown in Figure 43.
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Placement of Components
The recommended selection of component is as follows:
Place a bypass capacitor between the V DD and V SS
pins. A ceramic 1μF capacitor is suitable for most
applications. This component should be placed as
close as possible to the pins to reduce parasitic ele-
ments.
The bypass capacitor from V CC to COM supports both
the low-side driver and bootstrap capacitor recharge.
A value at least ten times higher than the bootstrap
capacitor is recommended.
The bootstrap resistor, R BOOT , must be considered in
sizing the bootstrap resistance and the current devel-
oped during initial bootstrap charge. If the resistor is
needed in series with the bootstrap diode, verify that
V B does not fall below COM (ground). Recommended
use is typically 5 ~ 10 Ω, which increases the V BS time
constant. If the votage drop of the bootstrap resistor
0
0
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900 1000
and diode is too high or the circuit topology does not
allow a sufficient charging time, a fast recovery or
Pulse Width [ns]
Figure 43. Negative V S Transient Chracteristic
Even though the FAN73933 has been shown able to
handle these negative V S tranient conditions, it is
strongly recommended that the circuit designer limit the
negative V S transient as much as possible by careful
PCB layout to minimize the value of parasitic elements
and component use. The amplitude of negative V S volt-
age is proportional to the parasitic inductances and the
turn-off speed, di/dt, of the switching device.
General Guidelines
Printed Circuit Board Layout
The layout recommended for minimized parasitic ele-
ments is as follows:
Direct tracks between switches with no loops or devia-
tion.
Avoid interconnect links. These can add significant
inductance.
Reduce the effect of lead-inductance by lowering
package height above the PCB.
Consider co-locating both power switches to reduce
track length.
To minimize noise coupling, the ground plane should
not be placed under or near the high-voltage floating
side.
To reduce the EM coupling and improve the power
switch turn-on/off performance, the gate drive loops
must be reduced as much as possible.
? 2009 Fairchild Semiconductor Corporation
FAN73933 ? Rev. 1.0.0
15
ultra-fast recovery diode can be used.
The bootstrap capacitor, C BOOT , uses a low-ESR
capacitor, such as a ceramic capacitor.
It is stongly recommended that the placement of compo-
nents is as follows:
Place components tied to the floating voltage pins (V B
and V S ) near the respective high-voltage portions of
the device and the FAN73933. NC (not connected)
pins in this package maximize the distance between
the high-voltage and low-voltage pins (see Figure 3.).
Place and route for bypass capacitors and gate resis-
tors as close as possible to gate drive IC.
Locate the bootstrap diode, D BOOT , as close as possi-
ble to bootstrap capacitor, C BOOT .
The bootstrap diode must use a lower forward voltage
drop and minimal switching time as soon as possible
for fast recovery or ultra-fast diode.
www.fairchildsemi.com
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| FAN7393A | 制造商:FAIRCHILD 制造商全称:Fairchild Semiconductor 功能描述:Half-Bridge Gate Drive IC |
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