参数资料
型号: FAN7602CM
厂商: Fairchild Semiconductor
文件页数: 11/18页
文件大小: 0K
描述: IC PWM FLYBACK ISOLATED CM 8SOIC
标准包装: 95
输出隔离: *
频率范围: *
输入电压: *
输出电压: *
功率(瓦特): *
工作温度: *
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: *
包装: 管件
To limit the output power of the converter constantly, the
power limit function is included in FAN7602C. Sensing
the converter input voltage through the Latch/Plimit pin,
the Plimit offset voltage is subtracted from 1 V. As
shown in Figure 22, the Plimit offset voltage is
subtracted from 1 V and the switch on-time decreases
as the Plimit offset voltage increases. If the converter
input voltage increases, the switch on-time decreases,
keeping the output power constant. The offset voltage is
proportional to the Latch/Plimit pin voltage and the gain
is 0.16. If the Latch/Plimit voltage is 1 V, the offset
voltage is 0.16 V.
5.1 Overload Protection (OLP)
The FAN7602C contains the overload protection
function. If the output load is higher than the rated
output current, the output voltage drops and the
feedback error amplifier is saturated. The offset of the
CS/FB voltage representing the feedback information is
almost zero. As shown in Figure 24, the CS/FB voltage
is compared with 50 mV reference when the internal
clock signal is HIGH and, if the voltage is lower than
50 mV, the OLP timer starts counting. If the OLP
condition persists for 22 ms, the timer generates the
OLP signal. The protection is reset by the UVLO. The
OLP block is enabled after the soft-start finishes.
1V
Power Limit
PWM+
Offset
Clock
CS/FB
FB
OLP
22ms
3 CS/FB
Offset
Timer
GND
On Time
Soft-Start
50mV
(a) Low Power Limit Offset Case
Figure 24. Overload Protection Circuit
1V
PWM+
CS/FB
GND
On Time
Power Limit
Offset
FB
Offset
5.2 Line Under-Voltage Protection
If the input voltage of the converter is lower than the
minimum operating voltage, the converter input current
increases too much, causing components failure.
Therefore, if the input voltage is LOW, the converter
should be protected. The LUVP circuit senses the input
voltage using the LUVP pin and, if this voltage is lower
than 2 V, the LUVP signal is generated. The comparator
has 0.5 V hysteresis. If the LUVP signal is generated,
(b) High Power Limit Offset Case
Figure 22. CS/FB Pin Voltage Waveforms
4. Burst-Mode Block
The FAN7602C contains the burst-mode block to reduce
the output drive block is shut down, the output voltage
feedback loop is saturated, and the OLP works if the
LUVP condition persists more than 22 ms.
V I N
the power loss at a light-load and no load. A hysteresis
comparator senses the offset voltage of the Burst+ for
the burst mode, as shown in Figure 23. The Burst+ is
the sum of the CS/FB voltage and Plimit offset voltage.
The FAN7602C enters the burst mode when the offset
1
?
+
2V/1.5V
LUVP
voltage of the Burst+ is higher than 0.95 V and exits the
burst mode when the offset voltage is lower than 0.88 V.
Figure 25. Line UVP Circuit
The offset voltage is sensed during the switch off time.
5.3 Latch Protection
Delay
Circuit
+
?
Burst+
Offset
3 CS/FB
The latch protection is provided to protect the system
against abnormal conditions using the Latch/Plimit pin.
The Latch/Plimit pin can be used for the output over-
voltage protection and/or other protections. If the Latch/
Plimit pin voltage is made higher than 4 V by an external
circuit, the IC is shut down. The latch protection is reset
0.95V/0.88V
Figure 23. Burst-Mode Block
when the V CC voltage is lower than 5 V.
5.4 Over-Voltage Protection (OVP)
If the V CC voltage reaches 19 V, the IC shuts down and
the OVP protection is reset when the V CC voltage is
lower than 5 V.
5. Protection Block
The FAN7602C contains several protection functions to
improve system reliability.
? 2009 Fairchild Semiconductor Corporation
FAN7602C ? Rev. 1.0.1
11
www.fairchildsemi.com
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