参数资料
| 型号： | FAN8303MX |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 9/12页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 2A 8SOIC |
| 标准包装： | 1 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.6 V ~ 20 V |
| 输入电压： | 5 V ~ 23 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 370kHz |
| 电流 - 输出： | 2A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 包装： | 标准包装 |
| 供应商设备封装： | 8-SOICN |
| 产品目录页面： | 1216 (CN2011-ZH PDF) |
| 其它名称： | FAN8303MXDKR |
Soft-Start
A capacitor, C SS , connected between the SS pin and
GND helps control the rate of rise on the output voltage.
When EN is HIGH and V IN is within the operating range,
a trimmed bias current charges the capacitor connected
to the SS pin, causing the voltage to rise.
The time it takes this voltage to reach 0.6V and the
PWM output to reach regulation is given by:
The system crossover frequency (f C ), where the control
loop has unity gain, is recommended for setting the
1/10th of switching frequency. Generally, higher f C
means faster response to load transients, but can result
in instability if not properly compensated.
The first step of the compensation design is choosing
the compensation resistor (R C ) to set the crossover
frequency by the following equation:
t RISE ( ms ) ≈ 0 . 1 ? C SS
(5)
R C =
2 π ? C OUT ? f C ? V OUT
G CS ? G EA ? V FB
(10)
where C SS is in nF.
Loop Compensation
The goal of the compensation design is to shape the
converter frequency response to achieve high DC gain
and fast transient, while maintaining loop stability.
FAN8303 employs peak current-mode control for fast
transient response and to help simplify the loop to a
one-pole and one-zero system.
where V FB is reference voltage and G CS is the current
sense gain, which is roughly the output current divided
by the voltage at COMP (2A/V).
The next step is choosing the compensation capacitor
(C C ) to achieve the desired phase margin. For
applications with typical inductor values, setting the
compensation zero, f Z2 , to below one fourth of the
crossover frequency provides sufficient phase margin.
Determine the (C C ) value by the following equation:
f P 1 =
C C =
π ? R C ? f C
The system pole is calculated by the equation:
1
2 π ? C OUT ? R L
where R L is the load resistor value (V OUT /I OUT ).
(6)
2
(11)
Determine if the second compensation capacitor (C A ) is
required. It is required if the ESR zero of the output
capacitor is located at less than half of the switching
f z 1 =
2 π ? C OUT ? ESR
< S
2 π ? C OUT ? ESR
(12)
The system zero is due to the output capacitor and its
ESR system zero is calculated by following equation:
1
(7)
The characteristics of the control system are controlled
by a series capacitor and resistor network connected to
frequency.
1 f
2
If required, add the second compensation capacitor
(C A ) to set the pole f P3 at the location of the ESR zero.
Determine the (C A ) value by the equation:
the COMP pin to set the pole and zero.
The pole is calculated by the following equation:
C A =
C OUT ? ESR
R C
(13)
f p 2 =
G EA
2 π ? C C ? A VEA
(8)
FAN8303
SW
V O
where:
G EA is the error amplifier transconductance (380μA/V);
A VEA is the error amplifier voltage gain (400V/V); and
C C is the compensation capacitor.
Zero is due to the compensation capacitor (C C ) and
resistor (R C ) calculated by the following equation:
PWM
modulator
COMP
R C
_
+
C A
0.6V
FB
f z 2 =
1
2 π ? C C ? R C
(9)
C C
where R C is compensation resistor.
Figure 16.
Block Diagram of Compensation
? 2008 Fairchild Semiconductor Corporation
FAN8303 ? Rev. 1.0.0
9
www.fairchildsemi.com
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