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参数资料
| 型号： | FC8001-X-C-K |
| 厂商： | C-MAC MICROTECHNOLOGY |
| 元件分类： | 光收发 |
| 英文描述： | FIBER OPTIC TRANSCEIVER, 830-860nm, 2500Mbps(Tx), 2500Mbps(Rx), MTP CONNECTOR |
| 文件页数： | 5/10页 |
| 文件大小： | 898K |
| 代理商： | FC8001-X-C-K |
TABLE II: TRANSCEIVER PIN DEFINITION (Continued)
Notes for table II
1. General: the transceiver can operate in ‘Legacy Mode’ without access to digitally stored built-in-test
(BIT) parameters, or operate in ‘BIT Mode’.
2. Ground is common inside the transceiver module.
3. Three isolated power supplies are maintained in the transceiver module. VDDA is a “quiet” supply to the
optical receivers (data and OTDR) as well as analog bias and measurement circuits. VDDB supplies the
receiver CML output section, the OTDR CML logic, the CMOS digital logic, and the micro controller. VDDC
supplies the laser drivers.
4. ENABLE/SDA (pin 5) functions to enable the laser driver output when the module is in legacy mode. In
this role it is asserted “active low”. When asserted, it enables the laser drive output. The default state is de-
active high through an internal 50kΩ pull-up resistor. The default, de-asserted state, disables laser drive
output for all transmit-channels. In BIT mode, ENABLE/SDA functions as the I2C serial data pin. A 4.7kΩ
pull-up resistor is switched in parallel with the pre-existing 50kΩ pull-up resistor, the pin may be driven
using an open-drain output by both the transceiver and the controlling device.
5. TD_IN_Px and TD_IN_Nx are the positive and negative transmit data inputs for channel ‘x’. These high
speed input pairs are differentially terminated with an internal 100Ω resistance. No external termination
is required. Differential signals are internally AC coupled to these pins.
6. Reserved pins (19, 20, 21, 22, and 27) should be left floating.
7. ST_RDY/SCK (pin 25) functions as the transceiver status ready indicator when the module is in legacy
mode. This pin includes an internal 4.7kΩ pull-up resistor. Upon transceiver power-up, pin 25 will be
pulled high, implying that the transceiver is NOT ready. After the transceiver has undergone internal BIT,
the ST_RDY/SCK pin will be set to a logical low value. The ST_RDY/SCK pin shall become active within
600ms of the power applied to the device coming within range. In BIT mode, ST_RDY/SCK functions as
the I2C serial clock pin and may be driven using an open-drain output by both the transceiver and the
controlling device.
Provisional Data Sheet
www.cmac.com
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