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参数资料
| 型号： | FCPL-70 |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 72 MHz, QCC16 |
| 封装： | ROHS COMPLIANT, SMT-16 |
| 文件页数： | 2/3页 |
| 文件大小： | 432K |
| 代理商： | FCPL-70 |
SELECTABLE FREQUENCY SYNTHESIZER
OPTIMIZED LOOP PARAMETERS
SURFACE MOUNT MODEL: FCPL-70
65 - 72 MHz
PERFORMANCE
PLOTS
HARMONIC SUPPRESSION
CLRWR
A
Att 30 dB
Ref 4 dBm
1 AP
30 MHz/
Start 50 MHz
Stop 350 MHz
* RBW 5 kHz
*
*
VBW 1 kHz
SWT 60 s
PRN
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
1
Marker 1 [T1 ]
3.30 dBm
69.711538462 MHz
2
Delta 2 [T1 ]
-12.69 dB
70.192307692 MHz
3
Delta 3 [T1 ]
-30.62 dB
140.384615385 MHz
4
Delta 4 [T1 ]
-42.46 dB
210.576923077 MHz
Comment: THIS ISTSSSSSSS
Date:
30.NOV.2005 10:32:28
REFERENCE SIDEBAND SUPPRESSION
CLRWR
A
Att 30 dB
Ref 4 dBm
2.5 MHz/
Center 69.99999199 MHz
Span 25 MHz
RBW 1 kHz
VBW 100 Hz
SWT 250 s
*
1 AP
PRN
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
1
Marker 1 [T1 ]
3.34 dBm
69.999991987 MHz
2
Delta 2 [T1 ]
-84.85 dB
-1.001602564 MHz
3
Delta 3 [T1 ]
-85.32 dB
1.001602564 MHz
4
Delta 4 [T1 ]
-85.47 dB
-7.532051282 MHz
Comment: THIS ISTSSSSSSS
Date:
30.NOV.2005 10:28:59
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