参数资料
| 型号： | FDMF8704 |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 9/11页 |
| 文件大小： | 0K |
| 描述： | IC MODULE DRIVER/FET 56MLP 8X8 |
| 标准包装： | 1 |
| 类型： | 高端/低端驱动器 |
| 输入类型： | PWM |
| 输出数： | 1 |
| 电流 - 输出 / 通道： | 32A |
| 电流 - 峰值输出： | 65A |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | -55°C ~ 150°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 56-MLP |
| 供应商设备封装： | 56-MLP（8x8） |
| 包装： | 标准包装 |
| 产品目录页面： | 1216 (CN2011-ZH PDF) |
| 其它名称： | FDMF8704DKR |
Module Power Loss Measurement and
Calculation
Refer to Figure 18 for module power loss testing method. Power
loss calculation are as follows:
(a) P IN = (V IN x I IN ) + (V CIN x I CIN ) (W)
(b) P OUT = V O x I OUT (W)
(c) P LOSS = P IN - P OUT (W)
PCB Layout Guideline
Figure 19. shows a proper layout example of FDMF8704 and
critical parts. All of high current flow path, such as V IN , VSWH,
V OUT and GND copper, should be short and wide for better and
stable current flow, heat radiation and system performance.
Following is a guideline which the PCB designer should
consider:
1. Input bypass capacitors should be close to V IN and GND pin
of FDMF8704 to help reduce input current ripple component
induced by switching operation.
I IN
2. It is critical that the VSWH copper has minimum area for
lower switching noise emission. VSWH copper trace should
also be wide enough for high current flow. Other signal routing
path, such as PWM IN and BOOT signal, should be considered
with care to avoid noise pickup from VSWH copper area.
3. Output inductor location should be as close as possible to the
FDMF8704 for lower power loss due to copper trace.
4. Snubber for suppressing ringing and spiking of VSWH
voltage should be placed near the FDMF8704. The resistor and
capacitor need to be of proper size for power dissipation.
5. Place boot diode, ceramic bypass capacitor and boot
capacitor as close to V CIN and BOOT pin of FDMF8704 in order
to supply stable power. Routing width and length should also be
considered
6. Use multiple Vias on each copper area to interconnect each
top, inner and bottom layer to help smooth current flow and heat
conduction. Vias should be relatively large and of reasonable
inductance.
I CIN
V IN
A
DISB
C VIN
VIN
DISB
VCIN
BOOT
A
C VCIN
V CIN
PWM
Input
PWM
HSEN
VSWH
C BOOT
L
I OUT
A
V OUT
CGND
PGND
V V O
C OUT
Figure 18. Power Loss Measurement Block Diagram
Figure 19. Typical PCB Layout Example (Top View)
FDMF8704 Rev. G
9
www.fairchildsemi.com
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