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| 型号： | FIN1031MX |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 3/6页 |
| 文件大小： | 0K |
| 描述： | IC DRVR QUAD 3.3V HS LVDS 16SOIC |
| 标准包装： | 1 |
| 类型： | 驱动器 |
| 驱动器/接收器数： | 4/0 |
| 规程： | LVDS |
| 电源电压： | 3 V ~ 3.6 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 标准包装 |
| 产品目录页面： | 1217 (CN2011-ZH PDF) |
| 其它名称： | FIN1031MXDKR |
3
www.fairchildsemi.com
FI
N1031
AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Note 3: All typical values are at TA = 25°C and with VCC = 3.3V.
Note 4: tSK(LH), tSK(HL) is the skew between specified outputs of a single device when the outputs have identical loads and are switching in the same direc-
tion.
Note 5: tSK(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction
(either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits.
Note 6: fMAX Criteria: Input tR = tF < 1 ns, 0V to 3V, 50% Duty Cycle; Output VOD > 250 mV, 45% to 55% Duty Cycle; all output channels switching in phase.
Note 7: Test Circuits in Figure 2 and Figure 4 are simplified representations of test fixture and DUT loading.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
(Note 3)
tPLHD
Differential Propagation Delay
0.8
1.4
2.0
ns
LOW-to-HIGH
tPHLD
Differential Propagation Delay
0.8
1.4
2.0
ns
HIGH-to-LOW
tTLHD
Differential Output Rise Time (20% to 80%)
RL = 100 , CL = 10 pF,
0.6
0.85
1.2
ns
tTHLD
Differential Output Fall Time (80% to 20%)
See Figure 2 and Figure 3 (Note 7)
0.6
0.85
1.2
ns
tSK(P)
Pulse Skew |tPLH - tPHL|
0.4
ns
tSK(LH)
Channel-to-Channel Skew
0.3
ns
tSK(HL)
(Note 4)
tSK(PP)
Part-to-Part Skew (Note 5)
1.0
ns
fMAX
Maximum Frequency (Note 6)
200
275
MHz
tZHD
Differential Output Enable Time from Z to HIGH
2.5
5.0
ns
tZLD
Differential Output Enable Time from Z to LOW
RL = 100, CL = 10 pF,
2.7
5.0
ns
tHZD
Differential Output Disable Time from HIGH to Z See Figure 4 and Figure 5 (Note 7)
3.2
5.0
ns
tLZD
Differential Output Disable Time from LOW to Z
3.4
5.0
ns
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