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| 型号： | FIN1048MTC |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 3/6页 |
| 文件大小： | 0K |
| 描述： | IC RCVR QUAD3.3V LVDS HS 16TSSOP |
| 产品变化通告： | Product Discontinuation 14/Mar/2011 |
| 标准包装： | 94 |
| 类型： | 接收器 |
| 驱动器/接收器数： | 0/4 |
| 规程： | LVDS |
| 电源电压： | 3 V ~ 3.6 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 16-TSSOP |
| 包装： | 管件 |
3
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FI
N1048
AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Note 3: All typical values are at TA = 25°C and with VCC = 3.3V.
Note 4: tSK(LH), tSK(HL) is the skew between specified outputs of a single device when the outputs have identical loads and are switching in the same direc-
tion.
Note 5: tSK(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction
(either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits.
Note 6: fMAX Criteria: Input tR = tF < 1 ns, VID = 300 mV, (1.05V to 1.35V pp), 50% duty cycle; Output duty cycle 40% to 60%, VOL < 0.5V, VOH > 2.4V.
All channels switching in phase.
Note A: All differential input pulses have frequency
= 10MHz, t
R or tF = 1ns
Note B: CL includes all probe and jig capacitances
FIGURE 1. Differential Receiver Voltage Definitions and Propagation Delay and Transition Time Test Circuit
TABLE 1. Receiver Minimum and Maximum Input Threshold Test Voltages
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
(Note 3)
tPLH
Propagation Delay LOW-to-HIGH
1.0
2.5
ns
tPHL
Propagation Delay HIGH-to-LOW
1.0
2.5
ns
tTLH
Output Rise Time (20% to 80%)
|VID| = 400 mV, CL = 10 pF,
0.7
1.2
ns
tTHL
Output Fall Time (80% to 20%)
RL = 1k
0.7
1.2
ns
tSK(P)
Pulse Skew |tPLH - tPHL|
See Figure 1 and Figure 2
0.4
ns
tSK(LH)
Channel-to-Channel Skew
0.3
ns
tSK(HL)
(Note 4)
tSK(PP)
Part-to-Part Skew (Note 5)
1.0
ns
fMAX
Maximum Operating Frequency
RL = 1k, CL = 10 pF,
200
375
MHz
(Note 6)
see Figure 1 and Figure 2
tZH
LVTTL Output Enable Time from Z to HIGH
6.0
ns
tZL
LVTTL Output Enable Time from Z to LOW
RL = 1k, CL = 10 pF,
6.0
ns
tHZ
LVTTL Output Disable Time from HIGH to Z
See Figure 3
6.0
ns
tLZ
LVTTL Output Disable Time from LOW to Z
6.0
ns
Applied Voltages (V)
Resulting Differential Input
Resulting Common Mode Input
Voltage (mA)
Voltage (V)
VIA
VIB
VID
VIC
1.25
1.15
100
1.2
1.15
1.25
100
1.2
2.4
2.3
100
2.35
2.3
2.4
100
2.35
0.1
0
100
0.05
00.1
100
0.05
1.5
0.9
600
1.2
0.9
1.5
600
1.2
2.4
1.8
600
2.1
1.8
2.4
600
2.1
0.6
0
600
0.3
00.6
600
0.3
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