参数资料
型号: FIN1048MX
厂商: Fairchild Semiconductor
文件页数: 1/6页
文件大小: 0K
描述: IC RCVR QUAD 3.3V HS LVDS 16SOIC
标准包装: 1
类型: 接收器
驱动器/接收器数: 0/4
规程: LVDS
电源电压: 3 V ~ 3.6 V
安装类型: 表面贴装
封装/外壳: 16-SOIC(0.154",3.90mm 宽)
供应商设备封装: 16-SOIC
包装: 标准包装
产品目录页面: 1217 (CN2011-ZH PDF)
其它名称: FIN1048MXDKR
2003 Fairchild Semiconductor Corporation
DS500588
www.fairchildsemi.com
September 2001
Revised August 2003
FI
N1048
3.
3V
L
V
DS
4-
Bit
Fl
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ough
H
igh
Speed
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al
Recei
ver
FIN1048
3.3V LVDS 4-Bit Flow-Through
High Speed Differential Receiver
General Description
This quad receiver is designed for high speed interconnect
utilizing Low Voltage Differential Signaling (LVDS) technol-
ogy. The receiver translates LVDS levels, with a typical dif-
ferential input threshold of 100mV, to LVTTL signal levels.
LVDS provides low EMI at ultra low power dissipation even
at high frequencies. This device is ideal for high speed
transfer of clock and data.
The FIN1048 can be paired with its companion driver, the
FIN1047, or any other LVDS driver.
Features
s Greater than 400Mbs data rate
s Flow-through pinout simplifies PCB layout
s 3.3V power supply operation
s 0.4ns maximum differential pulse skew
s 2.5ns maximum propagation delay
s Low power dissipation
s Power-Off protection
s Fail safe protection for open-circuit, shorted and termi-
nated conditions
s Meets or exceeds the TIA/EIA-644 LVDS standard
s Pin compatible with equivalent RS-422 and LVPECL
devices
s 16-Lead SOIC and TSSOP packages save space
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Function Table
H
= HIGH Logic Level
L
= LOW Logic Level
X
= Don’t Care
Z
= High Impedance
Fail Safe
= Open, Shorted, Terminated
Order Number
Package Number
Package Description
FIN1048M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
FIN1048MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Name
Description
ROUT1, ROUT2, ROUT3, ROUT4 LVTTL Data Outputs
RIN1+, RIN2+, RIN3+, RIN4+
Non-Inverting LVDS Inputs
RIN1, RIN2, RIN3, RIN4
Inverting LVDS Inputs
EN
Driver Enable Pin
EN
Inverting Driver Enable Pin
VCC
Power Supply
GND
Ground
Inputs
Outputs
EN
RIN+
ROUT
HL or Open
H
L
H
HL or Open
L
H
L
H
L or Open Fail Safe Condition
H
XH
X
Z
L or Open
X
Z
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