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参数资料
| 型号： | FIN224ACGFX |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 13/19页 |
| 文件大小： | 0K |
| 描述： | IC SERIALIZER/DESERIALIZER 42BGA |
| 标准包装： | 1 |
| 系列： | SerDes™ |
| 功能： | 串行器/解串器 |
| 数据速率： | 676Mbps |
| 输入类型： | LVCMOS |
| 输出类型： | LVCMOS |
| 输入数： | 22 |
| 输出数： | 22 |
| 电源电压： | 1.65 V ~ 3.6 V |
| 工作温度： | -30°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 42-VFBGA |
| 供应商设备封装： | 42-BGA |
| 包装： | 标准包装 |
| 产品目录页面： | 1217 (CN2011-ZH PDF) |
| 其它名称： | FIN224ACGFXDKR |
2006 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FIN224AC Rev.1.1.6
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Terminal Description
Note:
1. The DSO/DSI serial port pins have been arranged such that if one device is rotated 180 degrees with respect to the
other device, the serial connections properly align without the need for any traces or cable signals to cross. Other
layout orientation may require that traces or cables cross.
Terminal
Name
I/O Type
Number of
Terminals
Description of Signals
DP[1:20]
I/O
20
LVCMOS parallel I/O, Direction controlled by DIRI pin
DP[21:22]
I
2
LVCMOS parallel unidirectional inputs
DP[23:24]
O
2
LVCMOS unidirectional parallel outputs
CKREF
IN
1
LVCMOS clock input and PLL reference
STROBE
IN
1
LVCMOS strobe signal for latching data into the serializer
CKP
OUT
1
LVCMOS word clock output
DSO+ / DSI-
DSO- / DSI+
DIFF-I/O
2
CTL differential serial I/O data signals(1.)
DSO: Refers to output signal pair
DSI: Refers to input signal pair
DSO(I)+: Positive signal of DSO(I) pair
DSO(I)-: Negative signal of DSO(I) pair
CKSI+
CKSI-
DIFF-IN
2
CTL differential deserializer input bit clock
CKSI: Refers to signal pair
CKSI+: Positive signal of CKSI pair
CKSI-: Negative signal of CKSI pair
CKSO+
CKSO-
DIFF-OUT
2
CTL differential serializer output bit clock
CKSO: Refers to signal pair
CKSO+: Positive signal of CKSO pair
CKSO-: Negative signal of CKSO pair
S1
IN
1
LVCMOS mode selection terminals used to select frequency range for
the reflect, CKREF
S2
IN
1
DIRI
IN
1
LVCMOS control input used to control direction of data flow:
DIRI = “1” Serializer
DIRI = “0” Deserializer
DIRO
OUT
1
LVCMOS control output inversion of DIRI
VDDP
Supply
1
Power supply for parallel I/O and translation circuitry
VDDS
Supply
1
Power supply for core and serial I/O
VDDA
Supply
1
Power supply for analog PLL circuitry
GND
Supply
2
For ground signals (2 for BGA, 1 for MLP)
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相关代理商/技术参数 |
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| FIN224ACMLX | 功能描述:LVDS 接口集成电路 INTERFACE RoHS:否 制造商:Texas Instruments 激励器数量:4 接收机数量:4 数据速率:155.5 Mbps 工作电源电压:5 V 最大功率耗散:1025 mW 最大工作温度:+ 85 C 封装 / 箱体:SOIC-16 Narrow 封装:Reel |
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