参数资料
型号: FMS6145MTC14X
厂商: Fairchild Semiconductor
文件页数: 2/11页
文件大小: 0K
描述: IC DRIVER VIDEO FLTR 5CH 14TSSOP
标准包装: 1
类型: 驱动器
应用: 录音机,机顶盒
安装类型: 表面贴装
封装/外壳: 14-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 14-TSSOP
包装: 标准包装
产品目录页面: 1214 (CN2011-ZH PDF)
其它名称: FMS6145MTC14XDKR
IDT / ICS VCXO-TO-LVCMOS OUTPUTS
10
ICS81006AKI REV. B OCTOBER 8, 2008
ICS81006I
VCXO-TO-6 LVCMOS OUTPUTS
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LV
C
V
0
=4
.
5
1F
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3
.
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=6
.
9
2F
p
TABLE 6. VARACTOR PARAMETERS
FORMULAS
(
) (
)
() (
)
Low
V
S
L
Low
V
S
L
Low
V
S
L
Low
V
S
L
Low
C
_
2
_
1
_
2
_
1
+
+
=
(
) (
)
() (
)
High
V
S
L
High
V
S
L
High
V
S
L
High
V
S
L
High
C
_
2
_
1
_
2
_
1
+
+
=
6
0
1
0
1
0
10
1
2
1
2
1
)
(
+
+
=
C
TPR
Range
Pull
Total
High
Low
C
Low
is the effective capacitance due to the low varactor capacitance, load capacitance and stray capacitance.
C
Low
determines the high frequency component on the TPR.
C
High
is the effective capacitance due to the high varactor capacitance, load capacitance and stray capacitance.
C
High
determines the low frequency component on the TPR.
Absolute Pull Range (APR) = Total Pull Range – (Frequency Tolerance + Frequency Stability + Aging)
EXAMPLE CALCULATIONS
Using the tables and figures above, we can now calculate the
TPR and APR of the VCXO using the example crystal parameters.
For the numerical example below there were some assumptions
made. First, the stray capacitance (C
S1, CS2), which is all the excess
capacitance due to board parasitic, is 4pF. Second, the expected
lifetime of the project is 5 years; hence the inaccuracy due to
aging is ±15ppm. Third, though many boards will not require load
tuning capacitors (C
L1, CL2), it is recommended for long-term
consistent performance of the system that two tuning capacitor
pads be placed into every design. Typical values for the load tuning
capacitors will range from 0 to 4pF.
() ()
pf
C
Low
7
.
9
4
.
15
4
0
4
.
15
4
0
4
.
15
4
0
4
.
15
4
0
=
+
+
=
() ()
() (
)
pf
C
High
8
.
16
6
.
29
4
0
6
.
29
4
0
6
.
29
4
0
6
.
29
4
0
=
+
+
=
ppm
pF
TPR
5
.
226
10
4
8
.
16
1
220
2
1
4
7
.
9
1
220
2
1
6
=
+
+
=
TPR = ±113.25ppm
APR = 113.25ppm – (20ppm + 20ppm + 15ppm) = ±58.25ppm
The example above will ensure a total pull range of
±113.25 ppm with an APR of ±58.25ppm. Many times, board
designers may select their own cr ystal based on their
application. If the application requires a tighter APR, a crystal
with better pullability (C0/C1 ratio) can be used. Also, with the
equations above, one can var y the frequency tolerance,
temperature stability, and aging or shunt capacitance to achieve
the required pullability.
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