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参数资料
| 型号： | FMS6346MTC209 |
| 厂商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO20 |
| 封装： | LEAD FREE, MO-153AC, TSSOP-20 |
| 文件页数： | 8/10页 |
| 文件大小： | 616K |
| 代理商： | FMS6346MTC209 |
2006 Fairchild Semiconductor
www.fairchildsemi.com
FMS6346 Rev. 1.0.2
7
FMS6346
—
Six
Channel,
6th-Order
SD/HD
V
ideo
FIlter
Driver
The same method can be used for biased signals with the
addition of a pull-up resistor to make sure the clamp never
operates. The internal pull-down resistance is 800k
Ω
±20%, so the external resistance should be 7.5M
Ω to set
the DC level to 500mV. If a pull-up resistance less than
7.5M
Ω is desired, an external pull-down can be added
such that the DC input level is set to 500mV.
Figure 16. Biased SCART with DC-Coupled Outputs
The same circuits can be used with AC-coupled outputs if
desired, as shown in Figure 17.
Figure 17 DC-Coupled Inputs, AC-Coupled Outputs
Figure 18. AC-Coupled Inputs, AC-Coupled Outputs
Figure 19. Biased SCART with AC-Coupled Outputs
NOTE: The video tilt or line time distortion is dominated by
the AC-coupling capacitor. The value may need to be in-
creased beyond 220μF to obtain satisfactory operation in
some applications.
Power Dissipation
The FMS6346 output drive conguration must be consid-
ered when calculating overall power dissipation. Care
must be taken not to exceed the maximum die junction
temperature. The following example can be used to calcu-
late the FMS6346’s power dissipation and internal tem-
perature rise:
T
J = TA + Pd θJA
where P
d = PCH1 + PCH2 + PCHx
and P
CHx = Vs ICH - (VO
2
/R
L)
where
V
O = 2Vin + 0.280V
I
CH = (ICC / 6) +
(V
O/RL)
V
IN = RMS value of input signal
I
CC = 60mA
V
s = 5V
R
L = channel load resistance
Board layout can affect thermal characteristics. Refer to
the Layout Considerations section for more information.
Layout Considerations
General layout and supply bypassing play major roles in
high-frequency performance and thermal characteristics.
Fairchild offers a demonstration board, FMS6346DEMO,
to guide layout and aid device testing and characteriza-
tion. The FMS6346DEMO is a four-layer board with a full
power and ground plane. Following this layout congura-
tion provides the optimum performance and thermal char-
acteristics. For best results, follow the steps below as a
basis for high-frequency layout:
Include 10μF and 0.1μF ceramic bypass capacitors
Place the 10μF capacitor within 0.75 inches of the
power pin
Place the 0.1μF capacitor within 0.1 inches of the
power pin
For multi-layer boards, use a large ground plane to
help dissipate heat
For two-layer boards, use a ground plane that extends
beyond the device by at least 0.5 inches
Minimize all trace lengths to reduce series inductances
LCVF
Bias
Input
0.1μF
External video
source must
be AC coupled
500mV +/-350mV
75Ω
7.5MΩ
75Ω
DVD or
STB
SoC
DAC
Output
LCVF
Clamp
Inactive
0V - 1.4V
220uF
75Ω
DVD or
STB
SoC
DAC
Output
LCVF
Clamp
Active
0.1μF
0V - 1.4V
75Ω
220μF
LCVF
Clamp
Active
0.1
μF
External video
source must
be AC coupled.
500mV +/-350mV
220
μF
75Ω
7.5MΩ
75Ω
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