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参数资料
| 型号： | FMS6366MSA28X_NL |
| 厂商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO28 |
| 封装： | LEAD FREE, SSOP-28 |
| 文件页数： | 4/7页 |
| 文件大小： | 517K |
| 代理商： | FMS6366MSA28X_NL |
4
REV. 1B September 17, 2004
DATA SHEET
FMS6366
Applications
A typical application for the FMS6366 is shown in Figure 1.
Figure 1: Typical Application Diagram
Digital Delay Compensation
Figure 2: Digital Delay Compensation for
anti-alias 4:2:2 lters
The Chroma lters are one half the bandwidth of the
Luminance lter therefore the propagation delay time
through the Chroma lter is longer than the Luminance lter.
In the Standard Denition (SD) case, the Chroma lter
propagation delay is typically 60 nanoseconds longer than
the Luminance lter. This is three clock cycles at 54MHz so
it is easily corrected by adding digital delay as shown in
Figure 3 and illustrated as a shift register in Figure 2. In
the High Denition (HD) setting the Chroma lter propaga-
tion delay is typically 15 nanoseconds longer than the
Luminance lter. This is one clock cycle at 74.25MHz
so it is also easily corrected by adding digital delay to the
luminance path.
Functional Description
DC Levels
At any given time, the input signal’s DC levels must be
between 0.0V and 1.3V to utilize the optimal headroom
and to avoid clipping at the outputs. The Y channels accept
1Vpp signals with the sync tip at ground. The Pb, Pr and C
channels should be centered around 0.5V. This will ensure
that the lter will utilize the optimal headroom and avoid
clipping.
DC-Coupled Output Applications
The 220uF capacitor coupled with the 150
termination
forms a high pass lter that blocks the DC while passing the
video frequencies and avoiding tilt. Lower values such as
10uF cause unacceptable tilt in the output signal. By AC
coupling, the average DC level is zero. Thus, the output volt-
ages of all channels will be centered around zero.
DC coupling the output of the FMS6366 is allowable, but
not recommended. There are several trade-offs: The average
DC level on the outputs will be 2V. Each output will dissi-
pate an additional 40mW nominally. The application will
need to accommodate a 1V DC offset sync tip. Also, it is
recommended to limit one 150
load per output.
The FMS6366 is specied to operate with output currents
typically less than 50mA, more than sufcient for a dual
(75
) video load. Internal ampliers are current limited to
a maximum of 100mA and should withstand brief duration
short circuit conditions, however this capability is not guar-
anteed.
Driving Digital Pins
The FMS6366 digital inputs are compatible with most
3.3V and 5V logic. Verify that the Vih and Vil are within the
specied limits.
FMS6366
RSOURCE =
RT1 || RT2
2
3
PbINA
PbINB
4
5
Y1INA
Y1INB
6
7
PrINA
PrINB
8
YC / N_AUX
9, 10, 15, 17
NC
12
AUXIN
14
Y2IN
13
CIN
DAC
220
F
75
75
75
Video Cable
Y1OUT
23
75
75
75
Video Cable
PbOUT
22
75
75
75
Video Cable
Y2OUT
21
75
75
75
Video Cable
COUT
19
75
75
75
Video Cable
CVOUT
18
75
220
F
75
75
Video Cable
PrOUT
24
VCC
26
20
220
F
220
F
0.1
F
220
F
+5V
0.1
F1F
VSS
11
16
25
27
VSS VSS VSS
16
A_NB
23
HD / N_SD
RT2 = 75
RT1 = 75
RT2 = 75
RT1 = 75
RT2 = 75
RT1 = 75
RT2 = 75
RT1 = 75
RT2 = 75
RT1 = 75
RT2 = 75
RT1 = 75
Y
A/D
Shift
Register
8-10
Pr
A/D
8-10
Pb
A/D
8-10
Video
Processing
FMS6366
Luminance
Chroma
Propagation
Delay
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