参数资料
型号: FMS6410BCS
厂商: Fairchild Semiconductor
文件页数: 1/8页
文件大小: 0K
描述: IC FILTER VIDEO DUAL 8SOIC
标准包装: 95
类型: 视频滤波器
应用: 录音机,机顶盒
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOICN
包装: 管件
2004 Fairchild Semiconductor Corporation
www.fairchildsemi.com
October 2006
FMS6410B Rev. 1.0.2
FMS6410B
Dual-Channel
V
ideo
Dr
iver
s
with
Integrat
ed
Filt
er
s
and
Composite
V
ideo
Summer
FMS6410B
Dual-Channel Video Drivers with Integrated Filters and
Composite Video Summer
Features
7.1MHz fifth-order Y,C filters with composite summer
50dB stopband attenuation at 27MHz on Y, C, and CV
outputs
Better than 0.1dB flatness to 4.5MHz on Y, C, and CV
outputs
No external frequency selection components or clocks
< 5ns group delay on Y, C, and CV outputs
AC-coupled inputs
AC- or DC-coupled outputs
Capable of PAL frequency selection components or
clocks
0.3% differential gain with 0.2° differential phase on
Y, C, and CV channels
Integrated DC restore circuitry with low tilt
Lead-free SOIC-8 package
Applications
Cable and satellite set-top boxes
DVD players
Personal Video Recorders (PVR)
Video On Demand (VOD)
Description
The FMS6410B is a dual Y/C fifth-order Butterworth low-
pass video filter optimized for minimum overshoot and
flat group delay. The device also contains a summing cir-
cuit to generate filtered composite video.
In a typical
application, the Y and C input signals from DACs are AC
coupled into the filters. Both channels have DC restore
circuitry to clamp the DC input levels during video sync.
The Y and C channels use separate feedback clamps.
The clamp pulse is derived from the Y channel.
All outputs are capable of driving 2Vpp, AC or DC cou-
pled, into either a single or dual video load. A single
video load consists of a series 75
Ω impedance matching
resistor connected to a terminated 75
Ω line. This pre-
sents a total of 150
Ω of loading to the part. A dual load is
two of these in parallel, which presents a total of 75
Ω to
the part. The gain of the Y, C, and CV signals is 6dB with
1Vpp input levels. All video channels are clamped during
sync to establish the appropriate output voltage refer-
ence levels.
Block Diagrams
Figure 1. Block Diagram
Σ
gM
6dB
Sync Strip
Reference and
Timing
250mV
1
gM
+
250mV
4
6dB
8
6
5
3
7
VCC
YIN
CIN
GND
COUT
CVOUT
YOUT
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