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参数资料
| 型号： | FMS6501MSA28X |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 14/14页 |
| 文件大小： | 0K |
| 描述： | IC VIDEO SW MATRIX 12X9 28SSOP |
| 标准包装： | 1 |
| 类型： | 视频开关，12 输入，9 输出 |
| 应用： | 机顶盒 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SSOP（0.209"，5.30mm 宽） |
| 供应商设备封装： | 28-SSOP |
| 包装： | 标准包装 |
| 产品目录页面： | 1214 (CN2011-ZH PDF) |
| 其它名称： | FMS6501MSA28XDKR |
FMS6501
—
12
Input
/
9
Output
V
ideo
Switch
Matrix
with
I
nput
Clamp,
Input
Bias
Circ
uitry
,and
Output
Drivers
2004 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FMS6501 Rev. 1.0.4
9
Acknowledge
The data bytes transferred between the START and
STOP conditions from transmitter to receiver is unlim-
ited. Each byte of eight bits is followed by an acknowl-
edge bit. The acknowledge bit is a high-level signal put
on the bus by the transmitter, during which the master
generates an extra acknowledge-related clock pulse. A
slave receiver must generate an acknowledge after the
reception of each byte. A master receiver must generate
an acknowledge after the reception of each byte that has
been clocked out of the slave transmitter.
The device that acknowledges must pull down the SDA
line during the acknowledge clock pulse so the SDA line
is stable LOW during the HIGH period of the acknowl-
edge-related clock pulse (set-up and hold times must be
taken into consideration). A master receiver must signal
an end of data to the transmitter by not generating an
acknowledge on the last byte clocked out of the slave. In
this event, the transmitter must leave the data line HIGH
to enable the master to generate a STOP condition.
Figure 6. Acknowledgement on the I2C Bus
I2C Bus Protocol
Before any data is transmitted on the I2C bus, the device
that should respond is addressed first. The addressing is
always carried out with the first byte transmitted after the
start procedure. The I2C bus configuration for a data
write to the FMS6501 is shown in Figure 5.
Figure 7. Write a Register Address to the Pointer Register, Then Write Data to the Selected Register
SCL FROM
MASTER
DATA OUTPUT
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
START
condition
12
8
9
clock pulse for
acknowledgement
A6
A5
A4
A3
A2
A1
A0
19
R/W
D7
D6
D5
D4
D3
D2
D1
D0
1
9
ACK. BY
FMS6501
ACK. BY
FMS6501
FRAME1
SERIAL BUS ADDRESS BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
19
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
FMS6501
FRAME 3
DATA BYTE
SCL
SDA
START BY
MASTER
STOP BY
MASTER
SCL (CONTINUED)
SDA (CONTINUED)
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