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参数资料
| 型号： | FOD8012 |
| 厂商： | Fairchild Optoelectronics Group |
| 文件页数： | 4/12页 |
| 文件大小： | 0K |
| 描述： | OPTOCOUPLER BIDIR 3.3V 5V 8SOIC |
| 标准包装： | 3,000 |
| 电压 - 隔离： | 3750Vrms |
| 通道数： | 2，双向 |
| 电流 - 输出 / 通道： | 10mA |
| 数据速率： | 15Mbps |
| 传输延迟高 - 低 @ 如果： | 37ns |
| 电流 - DC 正向(If)： | ±10mA |
| 输入类型： | 逻辑 |
| 输出类型： | 推挽式/图腾柱 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SO |
| 包装： | 管件 |
Switching Characteristics
T A = -40oC to +110oC, 3.0V ≤ V DD ≤ 5.5V, unless otherwise specified.
Apply over all recommended conditions, typical value is measured at V DD1 = V DD2 = +3.3V, T A =25oC
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Data Rate
15
Mbit/s
t PHL
Propagation Delay Time
PW = 66.7ns, C L = 15pF
37
60
ns
to Logic Low Output
t PLH
Propagation Delay Time
PW = 66.7ns, C L = 15pF
40
60
ns
to Logic High Output
PWD
Pulse Width Distortion,
PW = 66.7ns, C L = 15pF (5)
3
15
ns
| t PHL – t PLH |
t PSK(CC)
Channel-Channel Skew
PW = 66.7ns, C L = 15pF (6)
12
25
ns
t PSK(PP)
t R
Part-Part Skew
Output Rise Time
PW = 66.7ns, C L = 15pF (7)
PW = 66.7ns, C L = 15pF
6.5
30
ns
ns
(10% to 90%)
t F
Output Fall Time
PW = 66.7ns, C L = 15pF
6.5
ns
(90% to 10%)
|CM H |
|CM L |
Common Mode Transient
Immunity at Output High
Common Mode Transient
Immunity at Output Low
V I = V DD1 , V O > 0.8V DD1 ,
V CM = 1000V (8)
V I = 0V, V O < 0.8V,
V CM = 1000V (8)
20
20
40
40
kV/μs
kV/μs
Notes:
1. No derating required.
2. 0.1μF bypass capacitor must be connected between Pin 1 and 4, and 5 and 8. The capacitors should be kept close
to the supply pins.
3. Device is considered a two terminal device: Pins 1, 2, 3 and 4 are shorted together and Pins 5, 6, 7 and 8 are shorted
together.
4. 3,750 VAC RMS for 1 minute duration is equivalent to 4,500 VAC RMS for 1 second duration.
5. PWD is equal to the magnitude of the worst case difference in t PHL and/or t PLH that will be seen for one channel
switching, while holding the other channel output at a low or high state, or while both channels are in synchronous
data transmission mode.
6. t PSK(CC) is equal to the magnitude of the worst case difference in t PHL and/or t PLH that will be seen between the two
channels within a single device.
7. t PSK(PP) is equal to the magnitude of the worst case difference in t PHL and/or t PLH that will be seen between any two
units from the same manufacturing date code that are operated at same case temperature, at same operating
conditions, with equal loads.
8. Common mode transient immunity at output high is the maximum tolerable positive dVcm/dt on the leading edge of
the common mode impulse signal, Vcm, to assure that the output will remain high. Common mode transient
immunity at output low is the maximum tolerable negative dVcm/dt on the trailing edge of the common pulse signal,
Vcm, to assure that the output will remain low.
?2010 Fairchild Semiconductor Corporation
FOD8012 Rev. 1.0.5
4
www.fairchildsemi.com
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